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Simulators >> Logic Simulators >> passing a string from CDF to a verilog-A model
https://designers-guide.org/forum/YaBB.pl?num=1135343801

Message started by Roi Carmon on Dec 23^rd, 2005, 5:15am

Title: passing a string from CDF to a verilog-A model
Post by Roi Carmon on Dec 23^rd, 2005, 5:15am

Hi andrew!!
Since you're the official GOD of Cadence (I had the pleasure to meet you at our Labs in Haifa Israel not too long ago), I want to ask you how do I pass a string varible from CDF form into Verilog-A model, and after this has been done, how do I manipulate it (comparing it to other string for instance).
I know that in the verilog-A vertion I have, there is NO support in string variables, but there will be on the 6.0 version.

Thanks andrew

Roi Carmon

Title: Re: passing a string from CDF to a verilog-A model
Post by Andrew Beckett on Dec 23^rd, 2005, 1:30pm

Hi Roi,

As we've been discussing this today via a service request, I'll continue the discussion there - but I'll probably post back here with an answer for the benefit of everyone else.

I'll do that after Christmas though...

Regards,

Andrew.