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Measurements >> Other Measurements >> clock jitter/phase noise for ADC testing
https://designers-guide.org/forum/YaBB.pl?num=1137685234

Message started by vivkr on Jan 19^th, 2006, 7:49am

Title: clock jitter/phase noise for ADC testing
Post by vivkr on Jan 19^th, 2006, 7:49am

Hi,

As is well-known, clock jitter directly limits the maximum SNR of a high-speed, high-resolution
ADC. In most references, it is mentioned that the jitter is treated like white noise in arriving at this
definition.

However, phase noise of any clock generator source is typically not white, but has a "skirt".

1. Is the calculation for peak SNR achievable still valid then? For instance, if I were to convert
the close-in phase noise information to jitter, could I use this number to estimate the peak SNR?

2. How can I do the above conversion? Manufacturers typically give close-in phase noise in
dBc/Hz at say a 1 kHz offset. How does one interpret this for finding rms jitteR?

3. Most importantly, how can I decide what sort and amount of phase noise is tolerable in my
test signal used for high-speed ADC testing?

If you wish you recommend any specific signal sources for >14bit and 10Msps range ADC testing,
then please feel free to do so as well.

Thanks
Vivek