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The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Design >> High-Power Design >> Behaviral modelling of dc-dc voltage converters https://designers-guide.org/forum/YaBB.pl?num=1138941612 Message started by navin_kumar on Feb 2nd, 2006, 8:49pm |
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Title: Behaviral modelling of dc-dc voltage converters Post by navin_kumar on Feb 2nd, 2006, 8:49pm Hi can any one give me good information about behaviral modelling od dc-dc voltage converters in spectre for top level behaviour analysis thanks & regrds navin |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by jbdavid on Feb 3rd, 2006, 12:17am What kind of information do you want? yes its very feasible.. Jonathan |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by navin_kumar on Feb 3rd, 2006, 12:52am Hi jonathan i want to do the stability analysis for the total current mode dc-dc voltage converter so i want information how we can model all the individual blocks in the dc-dc converter with verilog because i am havin spectre simulator i can model the blocks using verilog please give me information about any good thesis or papers thanks & regards navin |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Jess Chen on Feb 3rd, 2006, 10:16am Navin, You may want to check out the Forum discussion at http://www.designers-guide.org/Forum/YaBB.pl?num=1123068853 I assume you meant to write VerilogA instead of Verilog since you want to use Spectre. It is possible to simulate a power supply using Verilog and I can see how you might take that route for faster simulation, especially since many parts of today's power supplies are digital. However, if you want to do stability analysis, I would use Spectre and VerilogA. Most of the books I've seen on modeling power supplies were written for simple versions of SPICE that do not support VerilogA. I will post one later. I have not seen any books on modeling power supplies with VerilogA. Perhaps it's time for one. Are you interested in perfomance models, functional model, or some combination? Performance models simulate gain/phase margins etc. Functional models check connectivity and assume everything is ideal. You may also be interested in the books below. "Fast Analytical Techniques for Electrical and Electronic Circuits" by Vatche Vorperian. Cambridge University Press. 2002. Johnny C. Bennett, "Practical Computer Analysis of Switch Mode Power Supplies". It's published by CRC Press. -Jess |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by navin_kumar on Feb 4th, 2006, 10:23pm Hi jess chan i mean verilog A only, so that i can do it by using spectre i have to do the stabilityanalysis of CURRENT MODE DC -DC VOLTAGE CONVERTER USING PWM CONTROL can u give any information about the performance modelling of dc-dc voltage converter how to model each block of total dc-dc voltage converter thanks & regards navin |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Jess Chen on Feb 5th, 2006, 10:25pm I could list a bunch of references for you but most of them are out of print. I think your best bet is to pick up a book like Voperian's book (listed above) and check out pages 440-459. There are other books but again, like many of the original papers, they are probably out of print. Voperian's book is fairly recent. There may be other recent books on the subject. I do not have time to write out a detailed procedure, especially since I have not seen your schematic, but I can outline how I would attack the problem. Your analysis will most likely proceed in three steps: 1. Replace the switching elements with state space averaged models, usually DC/DC transformers. These can be easily implemented in VerilogA. If your inductor is always in continuous or discontinuous mode conduction, you can use a fairly simple model. If you want your model to be capable of switching conduction modes, your model will be more complicated. Be sure to include the input filter and any common mode EMI filters your system may have. There is another discussion in this section of the Forum where I give a few more details on state space averaging. 2. Based on your control (current mode control in your case), derive an expression for the duty cycle in terms of the input voltage, output current, output voltage, stabilizing ramp, and error amplifier voltage. You should be able to implement the control law in VerilogA too. 3. Identify and analyze the loops of interest. Current mode control involves multiple feedback loops. If you want to break all feedback loops, split the duty cycle node. You can assess the loops one at a time as long as you leave the loops closed for the next loop and keep track of closed loop right half plane poles. This procedure is called sequential loop closures or the sequential return difference method. I can give you references on the procedure but I must warn you that they are probably fairly obscure. Another approach is to compute the closed loop poles directly using Spectre's pz analysis. However, you will definitely want to check your results. The last time I used that feature, it gave a lot of extra poles and zeros. That is why I would probably use the sequential return difference method. If you are certain the inner loops are stable, you can leave those closed and concentrate on the outer loop, which is probably a voltage loop. In general, you should check your stability analysis against a step or impulse response. For AC stability analysis of one loop, I usually break the loop by inserting a zero voltage DC voltage source in the loop of interest, at a point where the upstream impedance (the source impedance), is much smaller than the downstream impedance (load impedance). There is a new Spectre feature called "stability analysis" that does not have such an impedance requirement. I tried it once and it seemed to work fine. However, in a multiloop system, you may have to resort to the large LC trick to break the loops that have not yet been analyzed without affecting the DC operating point. I apologize if my response is too short but that's all I have time for right now. Please let me know what parts are unclear and I will elaborate on them later. -Jess |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by navin_kumar on Feb 23rd, 2006, 4:22am Hi jess thanks for the information one more help i need is in this implementation i need to combile both the PFM AND PWMin asingle block for improving light load efficiency can u please give me some information about the switching the mode thanks & regards navin |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Jess Chen on Feb 23rd, 2006, 8:24am It's been several years since I've worked with power supplies and I am not familiar with the PFM acronym. As for modeling switch mode power supplies for light load, you probably need a dual-mode state space averaged model. Such a model runs very fast, is easily linearized by Spectre for AC analysis, and automatically switches between continuous and discontinuous modes. There may be more recent papers on such models but I can send you a couple of old ones if you are interested. These older papers were written for macro modeling, models built from SPICE primitives, but you may be able to convert them to VerilogA once you see how they work. However, I would recommend that you start from the state space averaging fundamentals. Look for papers by Drs. Middlebrook, Cuk, and I think, Ridley. I believe Dr. Fred Lee and/or some of his graduate students also wrote a few papers on modeling current mode converters. Once you understand the theory, implementation in VerilogA should be straightforward. -Jess |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by navin_kumar on Feb 23rd, 2006, 8:42pm Hi jess thanks for the information i will follow as u said and send me the links for the papers that u have thanks once again navin |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Jess Chen on Feb 24th, 2006, 12:08pm I will e-mail you a couple of papers. J. E. Chen and F. D. Rodriguez, "Duo-mode non-linear state space averaged SPICE model fo a current mode buck converter". Proceedings of the 1988 Applied Power Electronics Specialists Conference. F. D. Rodriguez and J. E. Chen, "A refined nonlinear averaged model for constant frequency current mode controlled PWM converters". IEEE Transactions on Power Electronics, Vol 6, No. 4, Oct 1991. -Jess |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by richard88 on Mar 5th, 2006, 9:13pm Jess, Can you comment on the differences, advantages between the PWM switch model (Voperian) and the canonical circuit model (middlebrook & erickson's book) ? If I wish to run ac sims to determine loop gain & phase, which is easier, better ? Is the Bennett's book talked about using switch model or canonical model ? Thanks. Jess Chen wrote on Feb 3rd, 2006, 10:16am:
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Jess Chen on Mar 6th, 2006, 4:14pm richard88, Can you be more specific about the Middlebrook/Erickson book? I'd like to be sure the canonical circuit is the one I remember. Is the canonical model in the book the same one that appeared in Wester's paper, Cuk's thesis, and a couple of PESC papers in the 70s? -Jess |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by richard88 on Mar 6th, 2006, 5:53pm Jess, I don't have the 70s papers, but I think the canonical form is that of the Cuk's thesis, an attachment : www.colorado.edu/~ecen5807/course_material/introduction2005.pdf]http://ece-www.colorado.edu/~ecen5807/course_material/introduction2005.pdf[/url] In Voperian's paper, he mentioned his model is more suitable for SPICE analysis. I wish to get comments on the pros and cons of each models. Particularly, which one is more commonly practise in the industry. I've constructed an ac model, I wonder if I can email you and get your comments on it ? If so, can I get your email id ? Thanks. Richard Jess Chen wrote on Mar 6th, 2006, 4:14pm:
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Jess Chen on Mar 6th, 2006, 6:51pm Richard, Yes, you can e-mail your AC model and I'll look at it. If you log into the Forum and click on my user name, a message window will pop up with my address already filled in. But in case you have trouble with it, my address is chennanga@yahoo.com. It helps if I can see the behavioral schematic so I don't have to reconstruct it from a netlist. -Jess P.S. As I recall, you were trying to use PAC to do a frequency domain loop gain analysis of an un-averaged SMPS model. Such an approach would be very powerful. Did it work? |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by richard88 on Mar 6th, 2006, 6:57pm Jess, Thanks for your response. Actually I have emailed you earlier on using that email address, wonder if you have received it ? I'll email with a diagram later. Yes, I have used PAC to run sims, it is powerful but it has a problem ... at times, the circuit can be difficult to converge. Very often I need to play around the integration method option to get it to converge. Also, we need to reduce as many components such as D-Flip Flop or else the convergence time can be very long. Thanks. Jess Chen wrote on Mar 6th, 2006, 6:51pm:
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Jess Chen on Mar 7th, 2006, 9:50am Richard, I e-mailed you my comments on the circuits you send me. Regarding the switch model and canonical model, they are essentially the same in my opinion. The only real difference from what I can tell is that the canonical circuit always puts a reference node at the bottom of the schematic, which forces one to sometimes include a second DC/DC transformer or a frequency dependent controlled source. However, Voperian's switch model does it with one, without having to introduce a zero in one of the controlled sources. The only time I would be extra careful when using switch models or canonical circuit models is when you switch current into a capacitor that has a significant amount of ESR. For example, if the output capacitor of a boost converter has a big ESR, the canonical circuit's state space equations do not match the true state space averaged equations. However, the ESR must be fairly large to matter. I have not analyzed Voperian's switch model in that example but if I were to guess without doing the analysis, I would suspect it works like the canonical circuit. If I get a chance, I'll check. Theoretically, there's probably a dual problem with inductors but I suspect the dominant loss in most inductors is a series element, which is not the dual problem. For practical circuits, I think the switch and canonical circuit models should give the same results. One key point is that if you are using a circuit simulator, you needn't linearize the circuit. As long as you have a time-invariant model, the simulator will linearize it for you. Also, you do not need to force everything into one canonical form. If you stick with the averaging basics, you can avoid introducing frequency dependent controlled sources that depend on operating point. -Jess |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Jess Chen on Mar 7th, 2006, 12:37pm I forgot to comment on Bennett's book. Bennett's book appears to use the non-linear model that when linearized, produces the canonical model. I have to take a closer look at Voperian's model but I suspect there is not any significant difference. -Jess |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Jess Chen on Mar 7th, 2006, 1:51pm If I understood Voperian's switch model, it has the same error as the canonical model with regard to capacitor ESR in a boost converter. The problem is that the circuit model (canonical or averaged switch) does not capture the true state space averaged equations for this example. The boost converter with a bad capacitor is somewhat of an academic exercise but it does nonetheless reveal one advantage of VerilogA over macromodels. With VerilogA, I can model the state space averaged equations directly; I do not need to synthesize a circuit model of the equations. If I get a free weekend, I'll try to post a paper elaborating on this. -Jess |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by richard88 on Mar 7th, 2006, 3:03pm Jess, Appreciate your answers. Do you mean you will post some examples on using verilogA to do the DCDC modeling ? That would be great ! I am using Cadence as simulator, I wonder if it matters on the syntax and I also don't know how to run with VerilogA in Cadence. I catch a glimpse of Bennett's book, it has a model that incorporates DCM and CCM together. That's neat. I ran the ac sim with esr on cap, it seems to reflect correctly with a zero, I don't get why you have concern about the esr ? Thanks. Jess Chen wrote on Mar 7th, 2006, 1:51pm:
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Jess Chen on Mar 7th, 2006, 4:20pm Yes am going to try to post a paper but first I need to get permission from my employer to use their computers and Cadence licenses. I am somewhat surprised that I have not heard of any such papers or books yet. I spent many years modeling power supplies the way Bennett describes, with SPICE primitives. It's not easy. I have written many RF models in VerilogA but have not applied VerilogA to power electronics because I was into RF by the time any simulators supported it. I did not read Bennetts approach to CCM and DCM mode in detail but at first glance, the schematics look like something me and a colleage published many years ago (see one of my earlier posts). Like Bennett, we also got many of our ideas from Dr. Bello, who Bennett mentions in his preface. We had gobbs of convergence problems. Perhaps Bennett's models are more robust. In any event, I think the VerilogA models will be fairly robust. Regarding the capacitor ESR, it is a small affect, more of an academic problem. The ripple probably becomes the more serious issue before the modeling problem becomes noticeable. Afterall, they do call the basic assumption the "low ripple approximation". When the boost capacitor's ESR becomes large, so does the ripple. -Jess |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by richard88 on Mar 7th, 2006, 4:31pm Jess, Why is modelling DCM important for the buck ? Esp ac model for DCM, I thought DCM is always one pole system and stable. Thanks. Jess Chen wrote on Mar 7th, 2006, 4:20pm:
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Jess Chen on Mar 7th, 2006, 5:01pm Richard, You're probably right about the system being more stable in the DCM but I'd still want to check it if my compensation network had more than two state variables. Furthermore, although stability is a key issue, it is not the only issue. If the bandwidth drops in the DCM, the audiosusceptibility, regulation, output impedance, and/or the input impedance could fall out of specification. If the converter can operate in the DCM these things should all be checked. For example, the supply may be required to respond to a transient load within some settling time. If the load goes from heavy to light such that the converter goes discontinuous, the transient response might be too slow. A state space averaged model that can change modes on the fly is very useful in studying such transients. -Jess |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by richard88 on Mar 7th, 2006, 5:31pm Jess, Thanks for the explanation, it makes sense. I've emailed you with question on compensation network and some other questions again, hope you don't mind. Thanks. Jess Chen wrote on Mar 7th, 2006, 5:01pm:
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Jess Chen on Mar 9th, 2006, 10:37am Richard, I responded to your e-mail. Please let me know if you did not receive it and I'll resend it. -Jess |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Tommy on Mar 20th, 2006, 8:56pm Jess Chen wrote on Mar 7th, 2006, 1:51pm:
Mr. Chen, Thanks. It will be really great if you post the paper. -Tom |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Eugene on Mar 21st, 2006, 1:23pm I've seen some questions regarding how to implement a DC/DC transformer in VerilogA. Below is a netlist of a simple, poorly designed buck converter. I slapped the model together just to demonstrate the VerilogA model of the state space averaged switch, which I've also included. The model does not check for conduction mode or duty cycle saturation but it is a start. The netlist runs AC and transient analyses. The loop gain can be computed by taking the AC gain from the minus terminal of V3 to the plus terminal of V3. The phase should be interpreted as phase margin. If I can figure out how to insert an image, I'll add a schematic. -Eugene Code:
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by richard88 on Mar 23rd, 2006, 8:56am Eugene, I'm new to verilogA usage, could you explain what is (or how to use) "electrical intrn" ... sounds like electrical is a keyword. Also, do you have anything on Boost converter ? I hope to look into voltage mode, and subsequently on current mode. I have a boost converter configuration, can I email you offline to discuss with ? Thanks, Richard |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Eugene on Mar 23rd, 2006, 4:12pm Hi Richard, "electrical" is indeed a key word. All inputs, outputs, variables, parameters, AND internal nodes must be declared. The "electrical intrn" statement defines an internal node that I use to sense output current without shorting the output pin to ground through the current probe and output voltage source. I will try to assemble a boost converter during a lunch break. I should be able to simply rearrange the pins on the switch model. You can e-mail me at wb6mcc@aol.com. -Eugene |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Eugene on Apr 2nd, 2006, 12:49pm I tried rearranging the circuit for a boost configuration, without changing the VerilogA model of the state space averaged switch. The boost model works fine in the time and frequency domains as long as there is no resistance in series with the main inductor. However, with just 100pOhms of resistance in series with the inductor, the circuit converges to the wrong DC operating point. If anyone's interested, I can post what I have. Otherwise I'll wait until I get around to fixing the series resistance problem. |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by akai_densha on Apr 3rd, 2006, 8:50pm Eugene, Thanks for the code!This runs well in Cadence I try to use the model with Silvaco tools. But I fail badly. The duty cycle input (net046) goes to over 800V! I tighten all tolerence but no luck :( Pls let me know your thoughts. Tanaka |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Eugene on Apr 4th, 2006, 8:42am Tanaka, Are you seeing DC or transient convergence problems? Are you trying to run the exact same circuit I posted? If so, then I would say there's either a typo, a problem with the tool (relative to Spectre), or some syntax difference between the tools. If you are trying to use the switch model with a different circuit, then I would recommend the following diagnostic steps: 1. Check the sign of the feedback. 2. Remove the input filter, if its a transient problem. 3. Try different input voltages, reference voltages, and/or loads. 4. Try adding code to the switch model to ensure the applied duty cycle lies between 0 and 1, or even some tighter range. I may post such lines later. 5. You could also try ramping up all independent sources from zero, either with a transient analysis or a swept DC analysis. I am not 100% sure but I think a swept Cadence DC analysis uses the previous swept result for the next initial guess. This trick worked for me just yesterday. It lets you "sneak up" on the correct operating points. There may even by an option to ramp sources automatically without setting up an explicit sweep. I am guessing here because I've never used the Silvaco tool. I would only touch the tolerances as a last resort. As I said in my last post, I am seeing convergence issues in a boost application of the switch. I am somewhat surprised by the problem, especially because the resistor that triggers it only needs to be 100 pico Ohms. I don't have much time to investigate it because it has nothing to do with my job. I'm looking at it just for personal interest. |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Eugene on Apr 4th, 2006, 11:12am Here's the boost circuit I'm trying. The 10pico Ohm resistor works but 100pico Ohms causes convergence errors. Anyway, the new switch model has duty cycle clamping. The model is not yet smart enough to change conduction modes on the fly. It's possible with macro models, I have just not tried it yet with VerilogA. The basic switch model is the same. I've just reconnected it to model a boost converter instead of a buck converter. -Eugene Code:
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by akai_densha on Apr 5th, 2006, 6:46pm Eugene-san, Thank you so-much! Actually I use same Verilog-A model provided by you. The problem is with verilog-A transformer model ( while useing in silvaco verilog-A). I try to simulate just the verilog-a code with iin=5V, dr=0.5V gg=0V & vout connected to the LCR network (same as the spectre netlist given by you). When I run a .op simulation, The voltage at "vout" is 0 and the current through the "vout" is zero & current drawn to terminal "iin" is zero, but voltage at "intrn" is 2.5! So, I suspect that the voltage and current at "intrn" node is not being given out to "vout" terminal. Please let me know your suggestions, & also Is there a way to implement this DC transformer without the intrn node? Thank you Masahiro Tanaka |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Jess Chen on Apr 5th, 2006, 7:21pm Masahiro-san, Yes, there is a version without the internal node (see below). Please let me know if this helps. -Jess Code:
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by akai_densha on Apr 5th, 2006, 8:44pm Chen-san, Thank you! This code gives me Matrix is singular problem! Tanaka |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Jess Chen on Apr 6th, 2006, 12:37am Tanaka-san, Do both switch models cause convergence problems? Does your input filter have any series resistance between the input voltage and switch? -Jess |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by akai_densha on Apr 6th, 2006, 1:14am Chen-san Thank you! onry second switch model give me convegence problem. The first switch model (2006/03/21) give me no convegence problem but give me problem in "intrn" node. I have no series resistance between input voltage and switch. Tanaka |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Jess Chen on Apr 6th, 2006, 9:25am Tanaka-san, I hope I am using the "san" address correctly. Please let me know if I am not. Does the switch work if you open the loop? i.e. try driving the dr pin with a 0.5 volt DC source. The DC output voltage should be exactly half the input voltage. In any event, I usually try to simplify such circuits to the point where any further simplification removes the problem. Sometimes the simplification process reveals the offending element so that you can then fix the problem. At the very least, the simplification process should produce a non-proprietary testcase you can send to your simulator vendor and/or post in this Forum. -Jess |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by akai_densha on Apr 9th, 2006, 6:09pm Chen-san "san" is a common practice in Japan. You are ok! The DC transformer dont work with .op simulation, The output is always zero. Ok , I try to fix the problem & send to this forum. The verilog-A in Silvaco refer to Accellera Verilog-AMS LRM version 2.2 , Sep 2004. I begin to wonder if this is different from Cadence version of Verilog-A in IC5.1.41? Tanaka |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Jess Chen on Apr 10th, 2006, 8:22am Tanaka-san, I can't help you with VerilogAMS or the Silvaco implementation. I do not have much experience with AMS and I have never used Silvaco tools. But from what I've seen in this Forum, if the problem is due to different interpretations of the language, the problem is usually syntactical and caught right away by the parser, before simulation ever starts. I'd be interested in seeing your code if you can post it. Also, someone else more familiar with AMS might be able to spot the problem. -Jess |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by akai_densha on Apr 10th, 2006, 5:42pm Chen-san, I dont get any simulation error. Only no result :( The code is same as given by you //DC DC Transformer `include "constants.h" `include "discipline.h" //discipline.h in Silvaco module DcDcX(gg, iin, vout, dr); inout gg, iin, vout; input dr; electrical gg, iin, vout, dr, intrn; analog begin I(iin,gg) <+ I(intrn,vout)*V(dr); V(intrn,gg) <+ V(iin,gg)*V(dr); // Nothing comes out at vout for .op. vout is connected to ground with a resistor end endmodule The second code is without the intrn node. //This code give me "Matrix is singular" error while simulation module DcDcX(gg, iin, vout, dr); inout gg; electrical gg; inout iin; electrical iin; inout vout; electrical vout; input dr; electrical dr; real dutycycle; analog begin if (V(dr)>1) dutycycle = 1; else if (V(dr)<0) dutycycle = 0; else dutycycle = V(dr); I(iin,gg) <+ I(gg,vout)*dutycycle; V(vout,gg) <+ V(iin,gg)*dutycycle; end endmodule |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Jess Chen on Apr 10th, 2006, 7:42pm Tanaka-san Could you also post the simplified schematic or netlist? Perhaps I could spot something with the rest of the testbench. -Jess |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by akai_densha on Apr 10th, 2006, 9:52pm Chen-San, This is netlist (The node "intrn" inside the verilog-A block is 2.5V but vout is zero) * C:\Silvaco\work\test Tue Apr 11 13:35:49 2006 ** * Gateway 2.4.1.R Spice Netlist Generator ** * Simulation timestamp: 11-Apr-2006 13:35:49.00 ** * * Schematic name: test * R1 GND NET2 1k V1 VDD GND DC 5 V2 NET1 GND DC 0.5 YVLGDCDCX1 GND VDD NET2 NET1 DCX_VLG * * Global Nodes Declarations * .GLOBAL VDD GND * * End of the netlist * * Markers to save * .SAVE ALL(I) ALL(V) **************************************** *VERILOG-A .VERILOG "dcdcx.va" **************************************** ******* ANALYSIS ****** .op * * ***** MODEL ***** * .MODEL DCX_VLG VLG MODULE = DcDcX .END |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Eugene on Apr 11th, 2006, 11:09am Tanaka-san, I tried your circuit with Spectre and saw the correct output voltage (2.5 Volts). The fact that with your simulator, the model with the internal node gives the correct voltage at the internal node but not at the output node tells me that your simulator is not handling current probes correctly. The model with the internal node should short the internal node to the output node. Instead, the simulator appears to leave the two nodes unconnected. Try the model below. This model should NOT work. Your simulator should complain of rigid loops, a shorted voltage source. If your simulator does not complain, then it is not handling current probes correctly but perhaps this trick works for your simulator. You do not have to remove the duty ratio clamping from your model. You only need to add the vsource line. -Eugene Code:
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Eugene on Apr 11th, 2006, 11:45am Tanaka-san, You could also try the model below, which should work with your simulator. The model below uses a small parameterized resistor to sense current. -Eugene Code:
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Eugene on Apr 11th, 2006, 6:38pm The resistive current sensor trick also solves the convergence problem with the boost converter when the input inductor has series resistance. -Eugene |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by akai_densha on Apr 12th, 2006, 6:08pm Eugene-san Thank you so much! Your solution solves problem. In my opinion, ideal current source series with voltage source caused problem. Tanaka |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Tommy on May 9th, 2006, 7:22am Eugene wrote on Mar 21st, 2006, 1:23pm:
Thanks, Eugene, But Iam not sure I understood this line -Tom |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Eugene on May 9th, 2006, 11:42pm Hi Tom, Consider a simple feedback system composed of two blocks (H and F) and an error amplifier. Let the forward gain, the gain from input to output when the feedback is disconnected, be H. Let the gain from the output to the negative input of the error amplifier by F. The closed loop transfer function, G, is G = H/(1+FH). The loop gain is FH. Let the phase of FH when |FH|=1 be x. Phase margin is defined as x-(-180) degrees. Note that FH does not include the sign inversion introduced by the feedback input of the error amplifier. However, when you insert a voltage source in the loop and compute the gain from one side of the source to the other, you are computing -FH because the signal propagated through the negative input of the error amplifier. Let the phase of -FH when |-FH|=1 be y. In general, the phase of -FH is the phase of FH+180. Since |-FH|=|FH|, y =x+180. Thus, y equals the phase margin of FH. Did this answer your question? -Eugene |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Tommy on May 11th, 2006, 1:18am Thanks a lot Eugene. This forum's a lifesaver :) |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by richard88 on Jun 19th, 2006, 3:36pm Eugene, Could you post the schematics of the boost and buck example ? It would be a good confirmation for my understanding. Thanks, Richard Eugene wrote on Apr 4th, 2006, 11:12am:
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Eugene on Jun 23rd, 2006, 11:22am I've attached the buck schematic...I think. |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Eugene on Jun 23rd, 2006, 11:23am Here's the boost schematic. |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by richard88 on Jul 8th, 2006, 4:04pm Hi Eugene, Thanks for the post. I've further questions ;D : Q1: The way you model the switch model is similar to what written in the paper written by Edwin van Dijk et al "PWM-Switch Modeling of DC-DC Converters", 1995 IEEE Trans of Power Electronics, am I right ? I find that it is important for the boost converter statement : if V(dr)>1==>dr=1, elseif V(dr)<0==> dr=0, or else the system won't work. Q2: I understand that you define the node intrn (for buck) is for convergence purpose. I just wonder how would the simulator knows that the node vout and intrn are connected together ? Because what we want to see is at the pin vout and not intrn. Is it via the statement "I(iin,gg) <+ I(intrn,vout)*V(dr);" ? Q3: For boost converter, since iin is defined as inout, it seems the current I(iin,gg) means current flowing out of node iin from node gg, is it correct ? By the way, how would the simulator knows that it is serving as output ? Q4 (most puzzling) : I simulated the boost system with the veriloga code. Plotting the magnitude and phase response across the vdc (acm=1) terminals, I got the waveform as attached. From my understanding, the complex pole of the power train is at (1/2*pi)*(vin/sqrt(L*vout)) which gives 159Hz, and the right hand plane zero is at (1/2*pi)*(Rload/L)*(vin/vout)^2 which gives 177kHz, the waveform I had shows gain peaking at 14kHz, I wonder how it can be explain. The waveform from simulating buck system is okay, but the boost system can be interesting. Thanks, Richard |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Eugene on Jul 13th, 2006, 1:29pm Hi Richard, Sorry for the delayed response. I've been really pressed for time. I have time now because I'm waiting for a simulation. A1: I am not familiar with the Dijk paper but it is possible the switch I used is based on that one. I think I learned of the universal switch from Voperian's book. Perhaps he got it from the Dijk paper. A2: Yes. If you don't assign a voltage across the current probe, like you might for a resistor, the voltage across the probe is zero. A3: VerilogA defines positive current as flowing into the ii node and out of the gg node. The ii node is declared as a bidirectional probe. However, whether it sources or sinks depends on the the duty ratio and I(intrn,vout). A4: I will have to answer this one later when I have more time to look at it. Sorry. |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by Eugene on Jul 17th, 2006, 1:33am Hi Richard, I finally got around to looking at your last question. I compute the zeros of the loop gain to be at {-3978.87, 176839.} Hz, and the poles to be at {-4533.75, -4497.21 - 15059.1*j, -4497.21 + 15059.1 *j} Hz and the crossover frequency to be at {f -> 191.568} Hz using Mathematica. This appears to be consistent with the Spectre simulation. I guess I don't see the issue. Without the integrator, the circuit is a third order system. The complex pole pair of the third order system lies at 15KHz, which explains the peaking. Also, please refer to my entry on 4/11. Replacing the current sensor with a resistive sensor makes the model more robust. In that case, there will be a slight voltage drop across the current probe but you can make the resistance small enough to make the voltage neglibible. -Eugene |
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Title: Behaviral modelling of dc-dc voltage converters Post by sonugoyal on Apr 24th, 2008, 2:19am hi all please provede me the verilog-a model for voltage regulator and bandgap reference, i have started to work on verilog-a one week back i need it please do help for me |
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Title: Re: Behaviral modelling of dc-dc voltage converter Post by sheldon on Apr 24th, 2008, 8:41am Sonugoyal, What are you trying to do? Since a Bandgap reference is just a fixed voltage why not use a voltage source? If you are using ADE, there are reference libraries with op-amp models: ahdlLib and bmslib. These libraries also include comparator models and are usually sufficient to get started with design. Are you looking for anything special in the models? That is, the models have limitations if you are trying to complex functional verification, for example, what happens when the op-amps inputs are higher than the power supply voltage. These types of conditions can happen in multiple supply power management designs and require more sophisticated models. Best Regards, Sheldon |
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Title: Re: Behaviral modelling of dc-dc voltage converters Post by ywguo on Jun 3rd, 2014, 12:02am Hi Eugene, What is the use of V2 in both buck converter and boost converter macro model? It is a pulse voltage source of 10s period, but the transient analysis stops at 10ms. Best Regards, Yawei |
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