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Design Languages >> Verilog-AMS >> Syntax error in case statement
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Message started by yongjin CHOI on Feb 3^rd, 2006, 9:16am

Title: Syntax error in case statement
Post by yongjin CHOI on Feb 3^rd, 2006, 9:16am

Hi,
As a beginner for learning verilog-A, I got a syntax error when I tried to implement 4-bit lookup table with a case statement. I couldn't figure out why Synopsys hspice 2005 complains my code "lookup.va" with the following errors. Is anyone suggesting me the reason or the simple way to implement 4-bit lookup table?
Any comments would be welcome.

Yongjin CHOI

hsp-vacomp: Synopsys HSPICE Verilog-A Compiler Version 1.26.111705.
hsp-vacomp: Copyright (C) 2005 Synopsys, Inc. All Rights Reserved.
hsp-vacomp:
hsp-vacomp: Error: Missing array index in using 'result'.
hsp-vacomp: ['lookup.va',30]

** error **
During Verilog-A Device processing:
Failed to compile the Verilog-A File, 'lookup.va'.

// Simple Lookup table 'lookup.va'

`include "disciplines.vams"
`include "constants.vams"

module lookup(out,in);
parameter real vdd = 2.5;
parameter real thresh = vdd/2;
parameter real tt=0.1n from (0:inf); // transition time of output signal
parameter real td=0 from (0:inf); // average delay from input to output

input [0:3] in;
output [0:3] out;

electrical [0:3] in;
electrical [0:3] out;
integer result [0:3];
real vout [0:3];
genvar i;

analog begin
for (i=0; i < 4; i=i+1) begin
if(V(in[i]) >= thresh) begin
result[i]= 1;
end else begin
result[i]=0;
end
end //for

case(result)
4'b0000 : begin vout[0]= 3; vout[1]= 0; vout[2]= 0; vout[3]= 0; end
4'b0001 : begin vout[0]= 0; vout[1]= 3; vout[2]= 0; vout[3]= 0; end
4'b0010 : begin vout[0]= 0; vout[1]= 0; vout[2]= 3; vout[3]= 0; end
4'b0011 : begin vout[0]= 0; vout[1]= 0; vout[2]= 0; vout[3]= 3; end
4'b0100 : begin vout[0]= 1; vout[1]= 0; vout[2]= 0; vout[3]= 0; end
4'b0101 : begin vout[0]= 0; vout[1]= 1; vout[2]= 0; vout[3]= 0; end
4'b0110 : begin vout[0]= 0; vout[1]= 0; vout[2]= 1; vout[3]= 0; end
4'b0111 : begin vout[0]= 0; vout[1]= 0; vout[2]= 0; vout[3]= 1; end
4'b1000 : begin vout[0]=-1; vout[1]= 0; vout[2]= 0; vout[3]= 0; end
4'b1001 : begin vout[0]= 0; vout[1]=-1; vout[2]= 0; vout[3]= 0; end
4'b1010 : begin vout[0]= 0; vout[1]= 0; vout[2]=-1; vout[3]= 0; end
4'b1011 : begin vout[0]= 0; vout[1]= 0; vout[2]= 0; vout[3]=-1; end
4'b1100 : begin vout[0]=-3; vout[1]= 0; vout[2]= 0; vout[3]= 0; end
4'b1101 : begin vout[0]= 0; vout[1]=-3; vout[2]= 0; vout[3]= 0; end
4'b1110 : begin vout[0]= 0; vout[1]= 0; vout[2]=-3; vout[3]= 0; end
4'b1111 : begin vout[0]= 0; vout[1]= 0; vout[2]= 0; vout[3]=-3; end
endcase

V(out) <+ transition(vout,td, tt);

end //analog
endmodule

Title: Re: Syntax error in case statement
Post by Geoffrey_Coram on Feb 6^th, 2006, 4:45am

It looks like the compiler doesn't like the fact that your case expression
case (result)
doesn't select a particular element of result. Perhaps the compiler thinks you have an "analog case statement" where the expression must be a genvar_expression? However, it seems to me that your case statement is legal syntax for 1364-Verilog, and thus should be accepted.

I have two warnings for other elements in your module:
1) transition() returns a real number, not an array, so you need to do
for (i=0; ,<4; i=i+1)
V(out[i]) <+ transition(vout[i], td, tt);

2) your bit orders are reversed; usually, one has
input [3:0] in;
output [3:0] out;
etc.

Title: Re: Syntax error in case statement
Post by Boris_Troyanovsky on Feb 8^th, 2006, 12:20pm

Hi Yongjin,

It looks as though your intent is to set individual bits within "result" to indicate whether V(in[i]) is above or below a certain threshold. However, declaring "result" as

integer result [0:3];

will give you an array of four integers, and not four bits. The compiler reports an error on the "case(result)" line because it expects to receive an integer value, rather than an array of integers (it could concatenate the integers together into a big bitfield, but I don't think that would give you the result that you expect based on your case-stmnt contents).

The way to address this issue is to simply use

integer result;

as your datatype, since a single integer contains more than four bits. You can then use bitwise ops, along with shifts, to set the proper bits as follows:

analog begin
result = 0;
for (i=0; i < 4; i=i+1) begin
if(V(in[i]) >= thresh)
result = result | (1 << i);
end //for

.... case stmnt goes here unchanged, etc.

Lastly, on your transition statement, you would want to loop through each of the values as follows:

for(i = 0; i < 4; i = i+1)
V(out[i]) <+ transition(vout[i],td, tt);

As Geoffrey mentions above, your bit order (most significant bit vs. least significant bit) may or (may not) be in the order that you intended, so that might be something to have a look at as well.

- Boris

Title: Re: Syntax error in case statement
Post by jbdavid on Apr 21^st, 2006, 2:14am

Alternatively you could declare result as
reg [3:0] result.
so that you get the logic values into the 4 bits..

but for that to work the complier (and simulator) would have to support verilog-AMS, not just the verilog-A subset..
Jonathan