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Other CAD Tools >> Physical Verification, Extraction and Analysis >> Figure Causing multiple stamped connections
https://designers-guide.org/forum/YaBB.pl?num=1140050855

Message started by velan on Feb 15^th, 2006, 4:47pm

Title: Figure Causing multiple stamped connections
Post by velan on Feb 15^th, 2006, 4:47pm

Hi,

I am university student currently learning Cadence tools. I use DIVA for DRC, Extract and LVS.

Process : TSMC18RF (0.18um)

I am currently doing layout of an 10 phase oscillator circuit. When I run DRC on my completed layout I get no errors. When I run Extract with the "Join nets with same name" switch ON and Parasitic RC Switch SET. I get the following errors :-/ :

Figure Causing Multiple Stamped Connections
Figure Having Multiple Stamped Connections

if i set the Parasitic RC switch OFF - that is if dont set any switches ( no parasitic extract ) I DONT get these errors or ANY errors.

My Design also passes the LVS succesfully

my design has following layout structure:

VDD Rail
====================
BUFFER Amplifiers
====================
GND Rail
====================
Differential Amplifiers
====================
VDD Rail
====================
Buffer Amplifiers
====================
GND Rail
====================

I googled these error messages and I found some explanations but I dont seem to violate any that is mentioned in these expalnations. Like I have connected the GND and VDD properly.

the divaEXT doesnt like me putting 2 separate ground Contacts. my Ground contacts are M1_SUB. if put them at separate places i get this error >:( . How do I go about resolving this issue? please help.

Title: Re: Figure Causing multiple stamped connections
Post by Andrew Beckett on Feb 18^th, 2006, 6:34am

As I've been responding to this over on news:comp.cad.cadence I won't answer it here too...

Andrew.