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Design Languages >> Verilog-AMS >> Performance/area tradeoff using several multiplier
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Message started by rahulfloyd on Feb 20^th, 2006, 5:38pm

Title: Performance/area tradeoff using several multiplier
Post by rahulfloyd on Feb 20^th, 2006, 5:38pm

Incase we use several, say 4, multipliers in parallel, to get a multiplication result in 1 clock cycle...as compared to a single cycle multiplier requiring 4 clock cycles to get the same result -
Would the increase in area on chip using the 4 parallel multipliers outweigh the improvement in performance (speed of operation) over the single cycle multiplier?

Title: Re: Performance/area tradeoff using several multip
Post by jbdavid on Apr 21^st, 2006, 2:10am

depends on your design criteria..
is area more important than the number of clock cycles.. or the other way around..
no "right" answer here untill you take your customers needs into account...
Jonathan