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Design Languages >> Verilog-AMS >> A verilog novice...
https://designers-guide.org/forum/YaBB.pl?num=1141684592

Message started by ness9660 on Mar 6^th, 2006, 2:36pm

Title: A verilog novice...
Post by ness9660 on Mar 6^th, 2006, 2:36pm

Im trying to learn verilog and Im having some problems. Mainly I dont really understand the difference between the different types of synsthesis, Behavioral vs RTL vs Gate level.

From my understanding Gate Level synthesis is just using the logic gate commands, e.g. AND OR XOR NOR, etc., so for example this would be a 2x1 multiplexer written in gate level:

Code:

module muxy(in1, in2, sel, out);
input in1;
input in2;
input sel;
output out;

wire a, b;

and(a, sel, in1);
and(b, ~sel, in2);
or(out, a, b);

endmodule

RTL and behavioral really dont make sense to me. From what Ive read behavioral synthesis is just creation using control flow statements (if, then, else, for, while, etc.), much like c/c++. So that a behavioral 2x1 mux would be something like:

Code:

module muxy(in1, in2, sel, out);
input in1;
input in2;
input sel;
output out;

if (sel==0 & in1=0 & in2=1)
assign out=1;
else if (sel=0 & in1=0 & in2=0)
assign out=0;
else blah blah blah

endmodule

Is that correct for behavioral?

As for Register Transfer Level, Im pretty lost, I dont see any other sort of coding style it could be.

Finally, Im having trouble finding good learning sources online, can anyone link me some good tutorials, more importantly example code for simple problems like 2x1 muxes?

Title: Re: A verilog novice...
Post by Marc Murphy on Mar 6^th, 2006, 7:02pm

You are misuing the term synthesis. Synthesis is the process by which the high-level RTL code gets a gate-level representation.

What you are talking about are two different styles of RTL.

I classify behavioral RTL as code that is functionally correct but can't be synthesized. And then there's synthesizable RTL.

If you want to be efficient, you write RTL that is then synthesized and results in gate-level RTL. In your second example you wrote RTL which should then be synthesized to give you something like your first example. Synthesis figures out the optimal logic representation, i.e. the gates to use, as well as the best drive strengths for the gates.

Anyhow, your understanding of the actual code looks OK but you have to get the ASIC flow straight in your head.

The Verilog may not be perfect (been a while) but you can write the MUX like this:

module muxy(in1, in2, sel, out);
input in1;
input in2;
input sel;
output out;
always @ ( sel or in1 or in2 )
if ( sel == 0)
out = in1;
else if ( sel == 1 )
out = in2;
end
endmodule

And there's a shorter way:

module muxy(in1, in2, sel, out);
input in1;
input in2;
input sel;
output out;
out = sel ? in2 : in1;
endmodule

The sensitivity list ensures changes show up on the output; we want combinational logic...no latches.

Cheers,
Marc