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Design Languages >> Verilog-AMS >> dither model
https://designers-guide.org/forum/YaBB.pl?num=1142512365

Message started by svensl on Mar 16^th, 2006, 4:32am

Title: dither model
Post by svensl on Mar 16^th, 2006, 4:32am

With respect to the post http://www.designers-guide.org/Forum/YaBB.pl?num=1142343700 I would like to know how to best dither a FM signal in VerilogA/AMS. So far I can only think of creating multiple delayed instances of the FM signal and then randomly selecting one tap with a mux.

1) ___|^-----|_____|^-----|____|^---|
2) __|^-----|_____|^-----|____|^---|
3) ____|^-----|_____|^-----|____|^---|
4) |^-----|_____|^-----|____|^---|

Essentially, the positive edges of the FM signal will phase shift randomly.

In VerilogA/AMS I tried using a absdelay() with a random shift generated using $rdist_uniform but when doing so the simulation will terminate saying that the delay has changed. Is a variable delay possible in VerilogA/AMS?

Are there any other ways to obtain a dithered FM signal?

Regards,
Sven

Title: Re: dither model
Post by Ken Kundert on Mar 16^th, 2006, 8:21am

Try using the noisy oscillator given in http://www.designers-guide.org/Analysis/PLLnoise+jitter.pdf in Listing 11 on page 36.

-Ken

Title: Re: dither model
Post by Ken Kundert on Mar 16^th, 2006, 8:25am

You can also find it in http://www.designers-guide.org/VerilogAMS/functional-blocks/osc/osc.va. You would use the oscillator with accumulating (or FM) jitter.

-Ken

Title: Re: dither model
Post by Ken Kundert on Mar 16^th, 2006, 8:27am

If you wanted to add a random delay to an input clock, use the transition function.

-Ken

Title: Re: dither model
Post by svensl on Mar 17^th, 2006, 1:02am

Thanks for the response Ken. When using the VCO including jitter I can dither the FM signal.
When only the FM signal is available I ended up using transition(n ? 1 : 0, dT, tt); where dT is created using $rdist_uniform. This works fine as a model but how would one implement this with real circuitry?

Thanks,

Ps. When looking at different examples from the Verilog-AMS section I noticed very different seed values for each application. Is there a reason for choosing the different seed values for different applicaitons or did you just pick a number?

Title: Re: dither model
Post by Ken Kundert on Mar 17^th, 2006, 9:07am

I am not familiar with the how jitter sources are implemented in practice. Conceptually it seems as if you would first have to decide whether you were looking for FM jitter or PM jitter. They differ in that in FM jitter the phase drifts without bound whereas with PM jitter there is a random variation of the phase but about a fixed mean.

If you are interested in FM jitter, you can produce it by feeding noise into the input of a VCO. If you are interested in PM jitter, pass a sinusoidal reference signal through a comparator where the threshold of the comparator is set by a noise source.

-Ken