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Design Languages >> Verilog-AMS >> Modeling high-z output in verilog-A
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Message started by steve_mac on Mar 18^th, 2006, 6:19am

Title: Modeling high-z output in verilog-A
Post by steve_mac on Mar 18^th, 2006, 6:19am

Hi,

How do i model high-z output in verilog-A ?

Currently I'm modeling it to output = 0, but it is causing conflict when i cascode them at top level (error = output connected to another output).

Currently the method i'm using is

:
:
vout = 0;
:
:

V(OUT) <+ vout ;
......

With what value should i replace the '0' with in order to get a high-z output?

Thanks a million for ur help !!!!!

Title: Re: Modeling high-z output in verilog-A
Post by Marq on Mar 20^th, 2006, 12:51am

Hi Steve,

A different approach might be to use indirect branch assignment (see LRM 2.2 section 5.3.2). In your case the statement:

V(OUT) <+ 0;

should be translated to:

V(IN): V(OUT) == 0;

Assuming there is a V(IN) and that it is (through the external circuit) connected to V(OUT) such that the simulator can solve for V(OUT) == 0.

If there is no such connection or no additional input (or inout) is available, you'll probably have to resort to either a very high output resistane (1TOhm) or connection through a controlled current source.

Title: Re: Modeling high-z output in verilog-A
Post by Eugene on Mar 20^th, 2006, 7:50am

For a high impedance output, are you sure you don't want to instead use

I(out) <+ 0;

?

Title: Re: Modeling high-z output in verilog-A
Post by Marq Kole on Mar 20^th, 2006, 8:09am

To prevent the "error = output connected to another output" it should also suffice to change the mode of the port OUT from "output" to "inout".

Title: Re: Modeling high-z output in verilog-A
Post by jbdavid on Apr 1^st, 2006, 10:03pm

In the case of a VOLTAGE output which I want to have as a resistor,
I usually,
V(iOut) <+ vout;
I(Out,iOut) <+ V(Out,iOut)*Rout..

- of course its even better to use a transition on Rout, and since its probably
to transition the EXPONENT of R not R itself.
Ron Vogelsong has written a number of modules like that ..
if you have access to Cadence SW, look in bmslib for sw_no
for a great example.
Jbd

Title: Re: Modeling high-z output in verilog-A
Post by Ken Kundert on Apr 2^nd, 2006, 12:09am

It would be more efficient to avoid the use of the internal node iOut and just use

Code:

V(out) <+ vout + Rout*I(out);

-Ken

Title: Re: Modeling high-z output in verilog-A
Post by jbdavid on Apr 21^st, 2006, 2:06am

maybe.. But I like to make the full branch explicit when I declare currents..
Jonathan