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Simulators >> AMS Simulators >> How to run verilog AMS designs...
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Message started by rajdeep on Mar 20^th, 2006, 5:34am

Title: How to run verilog AMS designs...
Post by rajdeep on Mar 20^th, 2006, 5:34am

Hi, can anybody help me to run verilog AMS designs from cadence icfb virtuso..?
It gives an error while running the simulation only that it cannot read the verilog AMS file!!

Thanx in advance

Title: Re: How to run verilog AMS designs...
Post by Geoffrey_Coram on Mar 22^nd, 2006, 9:01am

You're going to have to describe your problem better than that ...

What simulator are you using? Are you sure the V-AMS file is in the path? What about the header files? What exactly is the error message? From the simulator or from Virtuoso schematic environment?

Title: Re: How to run verilog AMS designs...
Post by rajdeep on Mar 23^rd, 2006, 12:56am

*Error* ERROR DETECTED IN NETLISTING, netlist bypass flag set.
*Error* Netlist type "VerilogAMSText" not handled by spectreS
component : current_monitor_ams
named : /I1
in cellview : test1/schematic
of library : Monitors
*Error* artIsCallablep: argument #1 should be either a string or a symbol (type template = "S") - nil[b][/b]

These are the errors coming when I'm trying to run a simulation where current_monitor_ams is a verilog AMS file.

I've tried to change the 'switch view' and 'stop list' in the environment from cadence analog environment. But it didnot help. Probably, I didnot give the right options. I've tried with spectreSverilog and SpectreSverilogams. In both cases it gives the following error:

"ERROR: Netlister: unable to descend into any of the views defined in the view list: "verilogams spectreSverilogams spice cmos_sch cmos.sch schematic veriloga ahdl" for instance V0 in cell test1."

I also want to add the followings:

1. VerilogA designs run fine.
2. Verilog AMS designs run fine whn I use ncvlog, ncelab and ncsim from command line.

Title: Re: How to run verilog AMS designs...
Post by Geoffrey_Coram on Mar 23^rd, 2006, 5:44am

Hope Andrew jumps in here ...

Do you have an analog block in your V-AMS module? I thought ncvlog only does digital Verilog, Spectre runs Verilog-A, and that you need AMS Designer to run Verilog-AMS if you really have A (analog) and MS (mixed-signal).

Title: Re: How to run verilog AMS designs...
Post by rajdeep on Mar 23^rd, 2006, 8:25pm

Yes, I surely have. And ncvlog -ams "*.vams" is the command that runs VAMS files.
What I want to know is how to set up the tool (cadence icfb, virtuoso) to run verilogAMS modules??
For mixed simulation something has to be done....which I do not know!!

CAN ANYBODY HELP?????

Title: Re: How to run verilog AMS designs...
Post by bernd on Mar 24^th, 2006, 1:59am

Some questions to make it more clear what you
want to do.

1. Which flow do you use in the Cadence DFIII environment to run AMS
Designer, do you use the AMS Plug-In the Hierarchy Editor
or do you use the Analog Artist integration of AMS?

2. Where do you set your switch and stop view list?

3. What's about this Error Msg.
*Error* Netlist type "VerilogAMSText" not handled by spectreS
and view names which contain 'spectreS'?
I'm pretty sure that AMS cna not run with spectreS (S == Spice socet),
it need Spectre direct in my opinion.

4. Can you explain you flow in a few steps?

Bernd

Title: Re: How to run verilog AMS designs...
Post by rajdeep on Mar 26^th, 2006, 10:18pm

The flow that I use:

1. I open a new cell view . I select VerilogAMS as the cell view. A text editor opens, I write my module there. I save the module, create a symbol for it.

2. Then I open another cell view, called composer-schematic. Here I instantiate my VerilogAMS module.

3. Now to simulate, I open Analog Environment from Tools>Analog Environment.

4. There if I click the 'Green light' to run simulation, I get those errors. I've tried to change the switch and stop list. But it did not work :-/

I need this desparately to run!! HELP!!!

Title: Re: How to run verilog AMS designs...
Post by bernd on Mar 27^th, 2006, 12:10pm

[edit]3. Now to simulate, I open Analog Environment from Tools>Analog Environment.[/edit]

The Analog Environment offers a variety of simulators, is it not
enough to create a VerilogAMS view to simulate with AMS.
Check under Setup->Simulator/Host, which Simulator is set.
Have you chosen AMS there?

[edit]4. There if I click the 'Green light' to run simulation, I get those errors. I've tried to change the switch and stop list. But it did not work[/edit]

It is also not enough to change the switch and stop list in the
environment settings of the Analog Environment you have to create
a so called configuration view in the Hierarchy Editor and partitioning
your design there.

Form my point of view it is not that straight forward to setup AMS Designer if your Design-Kit does not support this and your not familiar doing tool setup kind of things.
There will be sure a lot of more sticking points and I'm not quite
sure at which level you currently are?

Bernd

Title: Re: How to run verilog AMS designs...
Post by bernd on Mar 27^th, 2006, 10:24pm

I forgot to mention there is a AMS tutorial
refer to

Quote:

Virtuoso AMS Environment User Guide,
Chapter 2, Quick-Start Tutorial.
Or
your_install_dir/tools/dfII/samples/tutorials/AMS/README

Bernd

Title: Re: How to run verilog AMS designs...
Post by rajdeep on Mar 28^th, 2006, 5:55am

Thanks bernd, you have been of gr8 help. I'll surely try all these and get back.
1 more thing, I've tried to set the simulator as 'ams' in setup>Simulator/Host..but it gave a message saying that it can only be done if the view is config!! So, probably moving in the right direction. I also found this following link, it is huge, but seems like the one I need to follow...

http://www-bsac.eecs.berkeley.edu/~cadence/tools/mixed-mode.html

Title: Re: How to run verilog AMS designs...
Post by bernd on Mar 28^th, 2006, 9:57am

The URL you mentioned is explaining the "old",
coupled way of doing mixed signal simulations with
spectreVerilog and not the new single process approach
with AMS Designer. For your specific case spectreVerilog
can not deal with VerilogAMS just with VerilogA HDL.

The section "Partitioning the Design" might be useful to
explain how to create a config view and partitioning the design,
but be aware this is for the spectreVerilog simulation.

For AMS Designer you'd better work with the Cadence
Quick Start Tutorial I mentioned.

If you are interested in a coupled mixed signal
simulation with spectreVerilog I have also a document in
place which I can send to you if you drop me
your email in a personal message.

Bernd

Title: Re: How to run verilog AMS designs...
Post by Andrew Beckett on Mar 30^th, 2006, 5:31am

I think the reasons have been fairly well described here (sorry I'm so late jumping in...)

The primary one is that you cannot simulate a Verilog-AMS view in spectreS (or spectre for that measure) because these are analog simulators, not mixed signal simulators. That's why the spectreS interface is giving a netlisting error.

You need to use ams as the simulator in ADE. As it told you, you need to start from a config view - almost certainly you'd want to do this anyway, as it then gives you control over the views used (there's no view switching during netlisting in ams - the view switching is done during elaboration, and the config view controls the elaboration).

You'll still need to point at some connect modules - there's a Setup->Connect Modules menu for that.

Most importantly, read the documentation or tutorials that Bernd mentioned.

Regards,

Andrew.