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Design Languages >> VHDL-AMS >> textio
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Message started by coo848 on Mar 30^th, 2006, 6:16pm

Title: textio
Post by coo848 on Mar 30^th, 2006, 6:16pm

I use modelsim in vhdl design. I want to call data from fetalint.txt. my code is

use std.textio.all;

file infile: text is in "fetalint.txt";
variable ip1: integer range -4096 to 4095;
variable buf: line;
process
begin
while not(endfile(infile)) loop

readline(infile,buf);
read(buf,ip1);
W_data<=ip1;

wait until falling_edge(W_clock);

end loop;

After i compile it, it succeed with WARNING: C:/Program files/Modeltech_xe/examples/fetalfirV2_tb.vhd(53): Using 1076-1987 syntax for file declaration.

But the simulation is succeed.

Can i know how can i remove the warning?