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Design Languages >> Verilog-AMS >> Charge Pump with output voltage's limitation
https://designers-guide.org/forum/YaBB.pl?num=1144227523

Message started by jjun2003 on Apr 5^th, 2006, 1:58am

Title: Charge Pump with output voltage's limitation
Post by jjun2003 on Apr 5^th, 2006, 1:58am

Hi!

I am designing charge pump in PLL.

But, I don't know problem for designing charge pump.

I want to design charge pump that have a value of voltage limitation at output.

This is a source code.

module CP4 (vsrc, vref, siginc, sigdec, vout );

input siginc, sigdec;
inout vsrc, vref, vout;
electrical vsrc, vref, siginc, sigdec, vout;
parameter real iamp = 1m from [0:inf);
parameter real vtrans = 1.25 from [0:inf);
parameter integer cpmax = 5 from [0:inf);

integer inc_high;
integer dec_high;
integer selelec; // selection flag of electrical(1:potential, 0:flow)

analog begin
// @(initial_step) begin
// V(vout, vref) <+ V(vsrc, vref)/2;
// end

inc_high = V(siginc) > vtrans;
dec_high = V(sigdec) > vtrans;

if (V(vout, vref) > cpmax )
selelec = 1;
else
selelec = 0;

@(cross(V(siginc) - vtrans, 1)) begin
if (selelec)
V(vout, vref) <+ 2.5;
else
I(vsrc, vout) <+ iamp;
end

@(cross(V(sigdec) - vtrans, 1)) begin
if (selelec)
V(vout, vref) <+ 2.5;
else
I(vref, vout) <+ -iamp;
end
end
endmodule

This code is compiled but i can't simulated it for segentation fault.

Please, Help Me!!!! T T

Title: Re: Charge Pump with output voltage's limitation
Post by Geoffrey_Coram on Apr 5^th, 2006, 11:37am

jjun2003 -
Your Verilog-A compiler should *NOT* have allowed this model. You have contribution statements (<+) inside of an event (@), which is not allowed. (The contributions are not "persistent" meaning that, for timepoints when a crossing is not detected, your model as written would have no contributions at all.)

You need to re-write your model so that a variable is set inside the event.

Title: Re: Charge Pump with output voltage's limitation
Post by jjun2003 on Apr 5^th, 2006, 8:48pm

Thanks for your advice.

I could have referenced charge pump cell in ahdlLib library.
But I don't know solution to this cell, too.
This cell use a analog function, thus only control state of current.
I want to know how to limit output voltage in this cell.
this is charge pump code in ahdlLib.
I modified to select branch in this code.

I(vsrc, vout)<+ iout_val; // Original Code

if (V(vout) < 2.5)
I(vsrc, vout) <+ iout_val;
else
V(vout) <+2.5; // Modified code

But i still can't simulate it for convergence.
I thought that modifed code generates abrupt chage.
But I can't change abstol in PLL.

I appreciate your help. Thanks.

//--------------------
// charge_pump
//
// - Charge pump
//
// vout: output terminal from which charge pumped/sucked [V,A]
// vsrc: source terminal from which charge sourced/sunk [V,A]
// siginc,sigdec: Logic signal that control charge pump operation [V,A]
//
// INSTANCE parameters
// iamp = charging current magnitude [A]
// vtrans = voltages above this at input are considered high [V]

//
// MODEL parameters
// {none}
//
// This model can source of sink a fixed current, 'iamp'. Its mode
// depends on the values of 'siginc' and 'sigdec';
//
// When 'siginc' > 'vtrans', 'iamp' Amps are pumped from the output.
// When 'sigdec' > 'vtrans', 'iamp' Amps are sucked into the output.
// When both 'siginc' & 'sigdec' in same state - no current sucked/pumped.
//

module charge_pump(siginc, sigdec, vout, vsrc);
input siginc, sigdec;
inout vout, vsrc;
electrical siginc, sigdec, vout, vsrc;
parameter real iamp=0.5m from [0:inf);
parameter real vtrans = 2.5;

real iout_val;

//
// Current multiplier - returns direction that charge should be pumped
//
analog function real i_mult;
input inc;
input dec;
input vtrans;
real inc;
real dec;
real vtrans;

integer inc_high;
integer dec_high;

begin
inc_high = inc > vtrans;
dec_high = dec > vtrans;
i_mult = 0.0;
if (inc_high == dec_high) begin
i_mult = 0.0;
end else if (inc_high) begin
i_mult = 1.0;
end else if (dec_high) begin
i_mult = -1.0;
end
end
endfunction

analog begin
@ ( initial_step ) begin
iout_val = iamp*i_mult(V(siginc), V(sigdec), vtrans);
end

@ (cross(V(siginc) - vtrans, 0)) begin
iout_val = iamp*i_mult(V(siginc),V(sigdec),vtrans);
end
@ (cross(V(sigdec) - vtrans, 0)) begin
iout_val = iamp*i_mult(V(siginc),V(sigdec),vtrans);
end

I(vsrc, vout) <+ iout_val;
end
endmodule

Title: Re: Charge Pump with output voltage's limitation
Post by Geoffrey_Coram on Apr 6^th, 2006, 5:39am

I'd suggest trying a different approach for clamping the output voltage. What you've got now switches formulation (I-source to V-source) and could be doing so during Newton iterations and hence completely disrupting convergence.

Suppose you set the output current
I(vsrc, vout)<+ iout_val; // Original Code

and then provide a shunt path to suck away the current if the output voltage is too high:

if (V(vout) > 2.5)
I(vout) <+ 1e6*(V(vout) - 2.5);

Try this in a simple test case before you attach it to a full circuit. The 1e6 may need to be adjusted for your application.

Title: Re: Charge Pump with output voltage's limitation
Post by Geoffrey_Coram on Apr 6^th, 2006, 5:59am

jjun2003 wrote on Apr 5^th, 2006, 8:48pm:

@ (cross(V(siginc) - vtrans, 0)) begin
iout_val = iamp*i_mult(V(siginc),V(sigdec),vtrans);
end
@ (cross(V(sigdec) - vtrans, 0)) begin
iout_val = iamp*i_mult(V(siginc),V(sigdec),vtrans);
end

Are you sure you want the cross to detect transitions in both directions? I would expect that "siginc" would go high to say "start charging up" and then "siginc" could go low but the pump would keep putting out positive current until "sigdec" triggers. That is, I would make the second argument to cross a +1 to only detect positive-going transitions.

Title: Re: Charge Pump with output voltage's limitation
Post by Geoffrey_Coram on Apr 6^th, 2006, 6:31am

jjun -
Add the following lines to the module (after the I <+ transition... but before the "end" that closes "analog begin")

Code:

if (V(vout) > V(vsrc)) begin
I(vout) <+ clamp * 1e6 * (V(vout) - V(vsrc));
end else if (V(vout) < 0) begin
I(vout) <+ clamp * 1e6 * V(vout);
end

and then add

Code:

parameter integer clamp = 0 from [0:1];

after the other parameters.

Here's a netlist to try:

Code:

*
simulator lang = spectre

ahdl_include "charge_pump.va"

X1 (siginc sigdec vout vsrc) charge_pump iamp=1m
X2 (siginc sigdec vout_cl vsrc) charge_pump iamp=1m clamp=1

V1 (vsrc 0) vsource dc=5
V3 (siginc 0) vsource type=pulse val0=0 val1=5 delay=10n rise=1n fall=1n width=5
n period=10n
V4 (sigdec 0) vsource type=pulse val0=0 val1=5 delay=15n rise=1n fall=1n width=5
n period=10n

R1 (vout 0) resistor r=10k
C1 (vout 0) capacitor c=1f

R2 (vout_cl 0) resistor r=10k
C2 (vout_cl 0) capacitor c=1f

tran1 tran stop=30n

Run it, and notice how "vout_cl" is clamped between 0 and 5, whereas "vout" hits +/- 10.

Title: Re: Charge Pump with output voltage's limitation
Post by jjun2003 on Apr 6^th, 2006, 7:50pm

Thanks for your advice.

BUT I can't work it for bus error.

If i add your codes before (I(vsr,vout)<+transition...) I can run simulation.
(BUT vout_cl is LOW(=), unconditionally)
May you give me a full code?

Following that modified code.

parameter integer clamp=1 from [0:1];
...
// I(vsrc, vout) <+ transition(iout_val, tdel, trise, tfall); // This causes bus error!!!
if (V(vout) > V(vsrc)) begin
I(vout) <+ clamp*1e6*(V(vout)-V(vsrc));
end else if (V(vout) < 0) begin
I(vout) <+ clamp*1e6*V(vout);
end
I(vsrc, vout) <+ transition(iout_val, tdel, trise, tfall);

I always appreciate your help. ^^

Title: Re: Charge Pump with output voltage's limitation
Post by Geoffrey_Coram on Apr 7^th, 2006, 6:33am

Bus error? Then you need to update your simulator.

It really shouldn't matter if you have the transition() call before or after my code.