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Design Languages >> Verilog-AMS >> Verilog simulation: Can't descend into cell views
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Message started by aprior on Apr 6^th, 2006, 4:05pm

Title: Verilog simulation: Can't descend into cell views
Post by aprior on Apr 6^th, 2006, 4:05pm

I am having a problem trying to simulate with a verilog-a file. My steps where:

1. File->New->Create VIEW Name: veriloga TOOL: VerilogA-Editor
2. File->New->Create VIEW Name: symbol TOOL: Composer-Symbol

I edited the veriloga.va file and matched up the veriloga and symbol pins. The syntax seems to be okay.

I created a Hierachy as follows:

Library list: ap_sim ap_lib
View List: spectre cmos_sch schematic veriloga ahdl
Stop List: spectre veriloga

The schematic simulates just fine until I use the hierachy editor to switch in a verilog view. After clicking Netlist and Run I get the error:

ERROR: Netlister: unable to descend into any of the views defined in the view list: "veriloga" for instance I14 in cell SigmaDelta_sim. Either add one of these views to: Library: ap_lib Cell: firstorder_sigmadelta or modify the view list to contain an existing view.

I have another verilog file form an old employee that I copied into my lib. Removing my verilog symbol and placing in the that symbol causes no problem.

My Setup simulator/dir/Host simulator is "Spectre"

Note: I get the same problem if I remove a pin from the verilog code and symbol of the old cell. It as if I need to compile / update the cell somehow.

Help Please

Title: Re: Verilog simulation: Can't descend into cell vi
Post by ACWWong on Apr 7^th, 2006, 9:04am

after step 1) and you close the veriloga editor (and pass the parser) it should have automatically asked you to create the symbol. I think your problem may stem from the veriloga and symbol cdf's aren't synchronised properly.

try from the test bench schematic -> Design-> create view -> from cellview.

then fill in the form so it points to your veriloga view, and to view being symbol.

when you click ok, it will ask you to overwrite or modify your existing symbol, either will do the job.

hope this helps ....

Title: Re: Verilog simulation: Can't descend into cell vi
Post by aprior on Apr 7^th, 2006, 10:38am

The VI editor normally comes up, but I use another editor, that doesn't give me an indication that it passed the parser. I am now using the VI editor for all changes. I now get the passed syntax (parser) check message. Everything seems to be working fine now.

Thanks for the help

Title: Re: Verilog simulation: Can't descend into cell vi
Post by bernd on Apr 7^th, 2006, 11:08am

Strange, strange, I thought I would be related to the switch or stop view list,
but if the issue is solved when the parser gets invoked fine.

You can define your preferred editor with the variable
editor = "yourEditor"
e.g.
editor = "emacs"
or
editor = "nedit"

either direct in the Command Interpreter Window input line
or in your local .cdsinit file. Then the parser gets also invoked,
if you open the VerilogA view over the Library Manager.

Bernd

Title: Re: Verilog simulation: Can't descend into cell vi
Post by Andrew Beckett on Apr 11^th, 2006, 10:01pm

Yes, the parser is invoked to ensure that the "cdb" file (or "oa" file if using OpenAccess) is created for the verilog-a view. This contains information about the terminals and directions, and allows the netlister to view switch into the verilog-a view. Editing the file outside of DFII doesn't create this additional file in the cellView, and so it doesn't know how to switch into the verilog-a view.

As Bernd said, editing from within DFII will trigger the parser when the editor exits.

Regards,

Andrew.

Title: Re: Verilog simulation: Can't descend into cell vi
Post by jbdavid on Apr 21^st, 2006, 1:58am

Actually it will invoke the parse if the timestamp on the file is different after exiting the editor than it was before..
this is ALWAYS the case for vi if you :wq or :zz to exit..
but if you use nedit, open the file, click save, and exit it will NOT invoke the parser, because you didn't change the file,
so even if you ASK it to save.. it knows you have made no changes, and won't change the timestamp..
so you have to ACTUALLY add a space in a comment or something and THEN save to invoke the parser..
(or "touch" the file after you opened it.. )

When I create verilog-A from a perl script I copy it into the cell view, then set
editor = "touch" and "open" the files.. which "just" calls the parser (don't say yes if there are syntax errors!)
to build the extra stuff needed..
(then I set editor ="nedit" again.. )
there are Verilog-A pattern files (several years old) on the nedit web site at www.nedit.org .. still waiting for someone to contribute a similar set for SKILL and Verilog-A for VIM...
Nedit has a nice "incremental search bar" and gui driven search and destroy .. er replace..
and it has been my personal workhorse for the last 5+ years..
Jonathan