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Design Languages >> VHDL-AMS >> Fractional-N sigma-delta PLL Modeling
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Message started by oualkadi on Apr 12^th, 2006, 7:52am

Title: Fractional-N sigma-delta PLL Modeling
Post by oualkadi on Apr 12^th, 2006, 7:52am

Hell everybody,
I'm working in VHDL-AMS modeling of Fractional-N sigma-delta PLL, and I'm looking for some VHDL-AMS codes of sigma-delta modulators that can be used to do the modulation of PLL.
I'm also interested to talk and share information with people that work in this subject...
By the way, every help related to this subject (VHDL-AMS modeling of Fractional-N sigma-delta PLL) will be very helpful.

Best regards.

Oualkadi

Title: Re: Fractional-N sigma-delta PLL Modeling
Post by jbdavid on Apr 15^th, 2006, 2:04pm

I wrote one once in Verilog.. the logic of the sigma-delta modulator is quite simple..
for the PLL cases, I believe people most often have a semi-constant code "added" to the storage node on each
clock The carry bit of the adder is used to compare to the reference clock..
So for a div by 10.24 pll you might use an 8 bit adder, and add 25 on each VCO cycle..
use the carry bit to compare with the reference..

- of course often one will divide the Output with a few stages of fixed division, so that the S-D can use simpler, low speed logic.
But the beauty of all the schemes is that its simple register operations, so the range of possible configurations is quite large.
of course there are a few that have nice noise properties etc..

hope this helps.