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Measurements >> RF Measurements >> Measure post layout s-parameter
https://designers-guide.org/forum/YaBB.pl?num=1146091399

Message started by sren on Apr 26^th, 2006, 3:43pm

Title: Measure post layout s-parameter
Post by sren on Apr 26^th, 2006, 3:43pm

We are trying to measure the s-parameter from the extracted file after the layout by Cadence tool. Any of the methods (PSP,PSS,SP) require the proper ports. Could any one please tell me how to find the proper layout port or avoid the port to measure the s-parameter.

Thanks in advance.

Sren

Title: Re: Measure post layout s-parameter
Post by ACWWong on Apr 26^th, 2006, 11:55pm

Hi Sren,
The port is a testbench tool, so a layout view is not required. In the cadence tool it is analogLib/port.

Your extracted layout view of your circuit should be instantiated in a testbench and stimulated by the analogLib port (as well as things like vdc, idc etc.).

In the Cadence flow you can use the heirarchy editor (config view) to control the netlister so you can simulate the circuit schematic or extracted layout in the same testbench.

hope this helps

aw

Title: Re: Measure post layout s-parameter
Post by sren on Apr 27^th, 2006, 12:22pm

Thank you, aw.

I have not worked in the test bench environment so I am having trouble implementing your
recommendation. We have no trouble obtaining S-parameters in the schematic editor (not using
the test bench), but have not been able to set up the test bench to use either the schematic or
layout netlists and the required ports.

Anyway, thanks again.

Sren