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Design Languages >> Verilog-AMS >> PLI
https://designers-guide.org/forum/YaBB.pl?num=1147253110

Message started by MokoKoya on May 10^th, 2006, 2:25am

Title: PLI
Post by MokoKoya on May 10^th, 2006, 2:25am

Hello everybody,

I have created a verilogAMS testbench which contains many 'ifdef compiler directives. I want to be able to set which directive I want, run the simulation and then once complete reset the simulation with a diferent directive and start the simulation again.

I would like to do this automatically until I have simulated using all the different compiler directives, and run every test.

I am unsure on how to do this, and is using the PLI the correct way to achieve it?

I have never used PLI before and would apretiate any advice on the topic.

Thank you for taking the time of reading my query,
Andrew

Title: Re: PLI
Post by Andrew Beckett on May 15^th, 2006, 7:08am

Isn't this a matter of running ncvlog -define with the appropriate argument, elaborating, and simulating (or using ncverilog +define for the equivalent one-step flow solution) - and doing this for each compiler directive?

I don't think PLI would help - because you'd need to recompile - these are compiler directives, and so you need to alter what the compiler sees.

Andrew.