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Simulators >> AMS Simulators >> Hierarchical Verilog Code with SpectreVerilog
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Message started by schehrazi on May 19^th, 2006, 12:25am

Title: Hierarchical Verilog Code with SpectreVerilog
Post by schehrazi on May 19^th, 2006, 12:25am

I have this hierarchical Verilog code which instantiates some other modules in it. Now, I have created a symbol for this code and have placed it in a schematic. When I run a SpectreVerilog Simulation on this, I get an error messge saying

Module premitive ... not defined.

I suspect it does not recognize the instantiated module although it is in the same library as the higher level module. Does anyone know how to solve this problem?

Title: Re: Hierarchical Verilog Code with SpectreVerilog
Post by ACWWong on May 19^th, 2006, 10:49am

does the hierarchy editor (config view) pick up the verilog hierarchy ? it should list the verilog sub modules.

If this is not the case then this must be corrected. I haven't used spectreVerilog in a while, and as I am an analogue person, I guess I would create symbol and functional views for all the bits of verilog code in dfII format (cellname->viewname), then i think the config view will pick them up nicely.
To create the dfII format cellname->functional, I would use create cellview using verilog-editor in dfII to ensure the parser and auto-symbol generation are invoked. That way you'll know if you have any verilog code which the somewhat old verilogXL executable linked to in spectreVerilog doesn't like.

cheers

aw

Title: Re: Hierarchical Verilog Code with SpectreVerilog
Post by ACWWong on May 19^th, 2006, 10:58am

Oh one more thing to confirm is that the cellname is EXACTLY the same as the module name (first module declaration line).
so say cellname is Modulator in dfII, the verilog code must start:

module Modulator (....)

using

module modulator (...) would fail.

the compiler is very picky about cellnames matching the module names...

Title: Re: Hierarchical Verilog Code with SpectreVerilog
Post by schehrazi on May 19^th, 2006, 1:59pm

Hi,

Thank you for your reply. I actually fixed the problem after talking to a few groupmates of mine who were not in the lab last night. Here is the solution.
The hiererchy editor does not recognize the instantiated cells in a Verilog code (at least it did not do it in mine). I had to set the directory where the modules I instantiated were located manually. After opening Analog Environment, choose SpectreVerilog as the simulator. Then, go to Simulation -> Options -> Digital and write the path to your library in the "Library Directories". That will take care of the problems. Make sure, if you are instantiating any standard cells, you should add the path to that standard cell library as well. You might like to include some library files as well.