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Design Languages >> Verilog-AMS >> Creating SPICE Model
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Message started by 337see733 on May 21^st, 2006, 3:44am

Title: Creating SPICE Model
Post by 337see733 on May 21^st, 2006, 3:44am

Dear all,

I'm trying to find out how to create SPICE model for compact model. Not sure is this the right place to post ? Anyway, thanks in advanced.

Title: Re: Creating SPICE Model
Post by Geoffrey_Coram on May 24^th, 2006, 4:27am

This is as good a place as any to post -- I headed up the effort to add the compact modeling extensions in the Verilog-AMS LRM 2.3

Actually, you don't say in your post, but I assume you are planning to use Verilog-A.

But the best way to start is to look at the models posted on this site (http://www.designers-guide.org/VerilogAMS/) and use them as the basis for your model.

Title: Re: Creating SPICE Model
Post by 337see733 on May 24^th, 2006, 6:26pm

Thanks. I need to code it into SPICE so that it can run using SPICE machine. IS Verilog-A portable to SPICE ? or i need to code in other language? Thanks.

Title: Re: Creating SPICE Model
Post by Geoffrey_Coram on May 25^th, 2006, 4:41am

Tiburon (www.tiburon-da.com) has a Spice3f5 interface for Verilog-A.

There's a project (ADMS) on sourceforge that's supposed to connect Verilog-A to ngSpice, an open-source Spice clone, but my last experience with ADMS is that it's not fully mature.

Verilog-A can be run in Spectre, HSpice, Agilent ADS, Mentor Eldo, ...

Verilog-A is a lot nicer (higher-level) language for writing compact models. But if you need it to run in a particular Spice interface, you may need to code directly in C.

Title: Re: Creating SPICE Model
Post by A_Programmer on Jun 13^th, 2006, 1:51pm

I currently implemented my compact model as a subcircuit and it runs very very slow. I am trying to code it in C but it seems not to be a trivial task. Is coding it in Verilog A a wise alternative? Do you know, in terms of simulation speed, how inefficient a model coded in Verilog-A compared with one coded directly in C is?

Thanks a lot.

Title: Re: Creating SPICE Model
Post by Geoffrey_Coram on Jun 14^th, 2006, 4:06am

Good Verilog-A compilers can get their performance well under 2x the speed of hand-coded C. The ADMS folks said they had tuned a development version to get within 10% of the speed of the Berkeley C code for BSIM3.

Of course, that assumes that the hand-coding is correct :). If you have derivative errors in the C, then your simulation might not finish at all.

Title: Re: Creating SPICE Model
Post by A_Programmer on Jun 15^th, 2006, 3:32pm

Thanks a lot. Is the best way to learn Verilog-A by reading the book "The Designer's Guide to Verilog-AMS"?

Title: Re: Creating SPICE Model
Post by Geoffrey_Coram on Jun 16^th, 2006, 5:00am

DG to VAMS is a good book, but it covers all of Verilog-AMS, so if you're just interested in the analog subset and particularly compact modeling, then I would suggest

http://www.bmas-conf.org/2004/papers/bmas04-coram.pdf
http://www.bmas-conf.org/2004/presentations/bmas04-coram-preso.pdf

You can also learn a lot simply by looking at an existing model, of which there are a few you can download by clicking Verilog-AMS in the top right of these web pages.
http://www.designers-guide.org/VerilogAMS/

Title: Re: Creating SPICE Model
Post by A_Programmer on Jun 16^th, 2006, 10:46pm

;) Thank you so much. I will have fun with them I guess.