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Modeling >> Behavioral Models >> CML Modeling
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Message started by zeol on May 29^th, 2006, 6:26am

Title: CML Modeling
Post by zeol on May 29^th, 2006, 6:26am

Hi,

Is it possible to model transistor-level current mode logic circuits with behavioral models (e.g., Verilog-A) for spectre's transient simulation?

thanks!

Regards,
S. Lim

Title: Re: CML Modeling
Post by ACWWong on May 29^th, 2006, 4:00pm

zeol wrote on May 29^th, 2006, 6:26am:

Hi,

Is it possible to model transistor-level current mode logic circuits with behavioral models (e.g., Verilog-A) for spectre's transient simulation?

thanks!

Regards,
S. Lim

Yes.

Title: Re: CML Modeling
Post by zeol on May 30^th, 2006, 7:19am

Hi ACWong,

Could you give out a few pointers (e.g., references and/or books) on how i should go about modling the CML circuit. At the moment, I am trying to do it via Cadence's VSdE (a.k.a. Aptivia), but it is giving me trapezoid-like swing. I am interested in acurate modeling of all the harmonic tones, plus over/undershoots, as well as the input/output impedances.

Thanks!

Title: Re: CML Modeling
Post by ACWWong on May 30^th, 2006, 9:23am

There is a very good source of sample verilogA code on this website!

http://www.designers-guide.org/VerilogAMS/index.html

Also available are the models built into cadence installation path.

$Installation_root/tools/dfII/samples/artist/ahdlLib
$Installation_root/tools/dfII/samples/artist/rfLib

Usually one approaches the verilogA design from a behavioural viewpoint first, before adding inaccuarcies. So assuming that your CML circuit is actually behaving say as a frequency divider, one would start by coding the frequency divider nature, before adding limiting effects of finite input/output impedance/drive ability, distortion etc.

Title: Re: CML Modeling
Post by jbdavid on Aug 3^rd, 2006, 1:44am

Unfortunately none of those are going to do what you need.

what I find works well for Functional analysis is to model the output stage resistors, as resistors, and to control the current thru them from the behavior of the model..
but Generally speaking I use integer code (at least in Verilog-A) to model the function of the gate..
so while one can get decent accuracy of the transistion rise time etc from resistor and any line capacitance,
to talk of "harmonics" with "CML gates" doesn't work well, the gate will have a delay, and so you may get some harmonics thru multiple gates connected to the same power, or sharing a common bias node.. (signal to bias coupling I usually ignore..) But the gate itself cannot generate any, as it cant change state until the inputs cross a threshold..

For high speed functional checks I use Verilog-AMS, and am writing a paper on this very topic for the next BMAS conference. www.bmas-conf.org..
Jonathan