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Design Languages >> Verilog-AMS >> strange errors
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Message started by rajdeep on Jun 12^th, 2006, 8:06am

Title: strange errors
Post by rajdeep on Jun 12^th, 2006, 8:06am

Hello there, for the last 1 hr. I;ve been seeing this error and still unable to fix it..

Error found by spectre at time = 1.21302 us during transient analysis `tran'.
No convergence with minimum time step. Last acceptable solution computed
at 1.21302 us.

The values for those nodes that did not converge on the last Newton iteration
are given below. Also given is the manner in which the convergence
criteria were not satisfied in the following form:
Failed test: | Value | > RelTol*Ref + AbsTol

I(I11:out_flow) = 0 A, previously 0 A.
residue too large: | -5 V | > 5 mV + 1 uV
V(sw_in) = 0 V, previously 5 V.
update too large: | -5 V | > 0 V + 1 uV

To get rid of the I:out_flow problen I declared the out port of instance I11 of voltage discipline......still it gives the same error!!!

Plz help
Rajdeep

Title: Re: strange errors
Post by Ken Kundert on Jun 12^th, 2006, 11:06am

You should be looking at the models or circuit near the components and nodes mentioned to find things that would cause convergence problems. Look for discontinuities, floating nodes, etc.

-Ken

Title: Re: strange errors
Post by Geoffrey_Coram on Jun 13^th, 2006, 3:20am

I think you need to have a serious look at your module (since this is in the Verilog-AMS forum, and you wrote something about "voltage discipline," I'm guessing you're using Verilog-AMS). I think you probably have a switch branch you didn't know about or didn't implement properly, and/or some strange sensor branch.

Title: Re: strange errors
Post by rajdeep on Jun 13^th, 2006, 6:00am

no, i'm using verilogA only. Is voltage discipline not supported in verilogA?? My question was even after declaring a port as voltage ,errors related with flow at the port can arise? The port is not supposed to have a flow quantity!!

Title: Re: strange errors
Post by Ken Kundert on Jun 13^th, 2006, 11:33am

Verilog-A also supports voltage discipline.

At this point most simulators are not exploiting the fact that the flow is not needed for a signal-flow discipline to provide slightly faster simulation. Rather, they still internally formulate the equations to use flow even though they know that nothing will contributed to that flow.

-Ken