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Design Languages >> Verilog-AMS >> Compact Modeling extension
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Message started by A_Programmer on Jun 19^th, 2006, 6:43pm

Title: Compact Modeling extension
Post by A_Programmer on Jun 19^th, 2006, 6:43pm

I am using HSPICE Y-2006.03. Does it support the compact modeling extension? If not, is there any way I can output variables like gm, gd, and etc? Thanks a lot.

Title: Re: Compact Modeling extension
Post by Geoffrey_Coram on Jun 20^th, 2006, 7:42am

I believe the compiler supports it, but I forget the syntax for accessing (plotting) the values from within the simulator.

You could probably output the values with $strobe, of course, you'll want to be sure that ddx() works if you want gm.

Title: Re: Compact Modeling extension
Post by A_Programmer on Jun 22^nd, 2006, 1:39am

Since some of my analog functions take many input parameters (like 20), is there a way to implement some of them as "global variables" instead of passing 20 input variables to a function? Thanks a lot.

Title: Re: Compact Modeling extension
Post by Geoffrey_Coram on Jun 22^nd, 2006, 5:32am

A colleague at my company noticed that the "analog functions" in Verilog-AMS were strange beasts -- you have to declare them inside the module, but they don't have access to any of the other module-scope items, such as parameters. So, I don't have a good suggestion for you. I know some people use macros instead of functions because they find V-AMS functions lacking.