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Design Languages >> Verilog-AMS >> A very basic Verilog-A question
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Message started by A_Programmer on Jun 27^th, 2006, 1:54am

Title: A very basic Verilog-A question
Post by A_Programmer on Jun 27^th, 2006, 1:54am

What is the use of:

begin : something_something
.
.
.
end

Since there is no conditional statement preceding this block, do we use begin-end here simply for clarity? And, is something_something a comment again for clarity purpose too?

Thanks a lot.

Title: Re: A very basic Verilog-A question
Post by Geoffrey_Coram on Jun 27^th, 2006, 7:05am

begin-end can be used just for clarity. In this case, though, you have a "named block" (the "name" is something_something), and this allows you to declare items (parameters, variables) within the block.