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Design Languages >> Verilog-AMS >> Verilog A - CML file?
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Message started by A_Programmer on Jul 2^nd, 2006, 9:02pm

Title: Verilog A - CML file?
Post by A_Programmer on Jul 2^nd, 2006, 9:02pm

I am implementing a compact model for a device using Verilog A under HSPICE. When I check the Verilog-A log file, I find:

"The CML file is up to date. No compilation necessary."

What does it mean? Does it mean that, as long as I don't modify my Verilog A code, no compilation of the model is required even if I change the type of analysis?

Thanks.

Title: Re: Verilog A - CML file?
Post by Geoffrey_Coram on Jul 5^th, 2006, 7:51am

Yes, that's correct. The compilation should be independent of the analysis. You should also be able to change the parameter values that are passed to the module on the instance line without recompiling.