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Design Languages >> Verilog-AMS >> defining mixed-signal blocks
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Message started by vivkr on Jul 6^th, 2006, 7:43am

Title: defining mixed-signal blocks
Post by vivkr on Jul 6^th, 2006, 7:43am

Hi,

I am new to Verilog-A and especially to the mixed-signal aspect of it. I just tried to copy out a simple 1-bit DAC example as shown in the Cadence user manual for Verilog-AMS, and I get errors in compilation. The messages all read like:

Error: left operand of type node not supported for operator '*'
Error: right operand of type *undef* not supported for operator '+'

and so on...

The code which I directly copied down, cutting out a few nodes is shown below.
I don't quite understand why an example provided by Cadence would not compile.
Perhaps, this is a very trivial question, but I would be glad to have suggestions. I am
trying to build a Verilog-AMS interface for my analog block to a Verilog code, and SpectreHDL, which I normally use for analog modelling is not supported for mixed-signal simulations with AMS-Designer.

Thanks
Vivek

`include "constants.vams"
`include "disciplines.vams"

module DACMacroExample(b0, b1, b2, b3, compSig);
input b0, b1, b2, b3;
output compSig;

logic b0, b1, b2, b3;
electrical compSig;

parameter real refVolt = 2.5;

analog
begin
V(compSig) <+ (refVolt/16)*(b0 + 2*(b1 + 2*(b2 + 2*b3)));
end
endmodule

Title: Re: defining mixed-signal blocks
Post by vivkr on Jul 6^th, 2006, 8:03am

Hi,

I was able to find the source of the errors. I had been creating the cellviews as "veriloga" instead of "verilogams" and hence there was some syntax incompatibility (I think). Now, I have a block. Let me see how I can use AMS-Designer now.

Regards
Vivek

Title: Re: defining mixed-signal blocks
Post by jbdavid on Aug 3^rd, 2006, 4:33am

There is DEFINITELY a difference between Verilog-A and Verilog-AMS..
Verilog-A is the ANALOG ONLY subset of the language.. hence its usefulness to the compact modelling community and analog designers..using only Spectre