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Design Languages >> Verilog-AMS >> cap model
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Message started by mkaragou on Jul 19^th, 2006, 5:37am

Title: cap model
Post by mkaragou on Jul 19^th, 2006, 5:37am

I would like to implement a model for the capacitance Cgs that is valid in all regions of operation of a MOS transistor in Verilog-A/MS.

The capacitance model that I want to implement is simplified and is used for hand calculations, normally

Now I want to compare how well it fits with the more precise capacitance expressions of the BSIM model.

So I would like to perform a parametric DC simulation in spectre and to plot the cgs value of the bsim model
by using the OP function of the calculator and compare it with a plot of the capacitance value of my Verilog-A/MS model.

The problem is that in Verilog-A/MS the capacitance value is not calculated directly, but instead the charge is calculated
and than differentiated to get the current contribution of the cap.

q= bla* bla*exp( bla);
i<+ddt(q);

So how can I compare the cap value of the BSIM model with the cap value of my Verilog - A/MS model?

Title: Re: cap model
Post by Geoffrey_Coram on Jul 19^th, 2006, 11:30am

I believe Spectre's ac analysis can be done with a dc sweep, specifying a single frequency for the ac part.

Set an ac magniture for a voltage source on the source terminal, and measure the imaginary part of the gate current.

Be sure to turn off drain/source resistance.

Title: Re: cap model
Post by mkaragou on Jul 19^th, 2006, 11:42pm

Thanks a lot for the hint!

The cap is my first Verilog -A/MS model and I am quite impressed of the capabilities of modeling that are possible by using this language!

I have read in the book of Ken and Olaf that it is possible to model noise with Verilog-A/MS but the Cadence AMS simulator offers only a DC, AC and transient but no noise analysis.

Do you know how to perform a noise analysis with the Cadence simulator?

Title: Re: cap model
Post by Geoffrey_Coram on Jul 20^th, 2006, 4:14am

I know how to run a noise analysis in spectre, but not in AMS Designer.
spectre -help noise
should give you all you need to know. It's pretty much the same as ac, but you need to specify an output node for measuring the noise.

-Geoffrey

Title: Re: cap model
Post by mkaragou on Jul 20^th, 2006, 4:53am

Is spectre able to simulate Verilog -A/MS modules? I did not know that. I tried it once but the nelister told me that it does recognize
the view type verilogams. So I switched to the AMS simulator!

Title: Re: cap model
Post by bernd on Jul 20^th, 2006, 5:15am

Spectre is a analog circuit simulator and is not able to simulate
VerilogAMS.
You have to switch either to AMS Designer or any other Mixed-Signal
simulator who is able to simulate VerilogAMS models or you can model
analog behaviour with VerilogA only and simulate it with Spectre.

I'm quite certain that you have no noise or transient noise
analysis in AMS Designer.

Bernd

Title: Re: cap model
Post by mkaragou on Jul 20^th, 2006, 7:44am

So when I have used only Verilog A features in my model file, I could just change the name of my view
from verilogams to veriloga, change the config file to use the veriloga view and than simulate it with spectre!

I checked this and it worked fine, thanks Geoffrey & Bernd :)