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Design Languages >> Verilog-AMS >> period stretcher / expander
https://designers-guide.org/forum/YaBB.pl?num=1154013304

Message started by svensl on Jul 27^th, 2006, 8:15am

Title: period stretcher / expander
Post by svensl on Jul 27^th, 2006, 8:15am

Hello all,

I have a frequency modulated signal. I would like to determine each period of the FM signal, then determine whether it is above or below a reference period. Based on that decision I would like to either multiply this period with a constant factor or divide by it. Having done that I want to generate a new signal based on the determined periods.
In summary, I would like to amplify the frequency modulation of a FM signal by either increasing or decreasing each period.

I am not even sure whether this can be done with a real circuit. But, at the moment I want to use VerilogA to implement the above.
The period determination and scaling is not an issue. I was wondering how I can create a new signal based on the obtained period information. I guess I need to create 1 period of this new signal, and then add on another just determined new period.

Can anyone suggest a way?

Regards,
Sven

I am using the following code to determine the periods of a FM signal.

Code:

`include "disciplines.vams"
`include "constants.vams"

module fmeasure (in, out);
input in; voltage in;
output out; voltage out;
real last_time, current_time, freq;

analog begin

@(initial_step)begin
last_time = 0.0;
freq = 0.0;
end

@(cross(V(in) -0.5, 1)) begin
current_time = $abstime;
if (last_time > 0.0)
freq = 1.0 / (current_time - last_time);
last_time = current_time;
end
V(out) <+ freq;
end
endmodule

Title: Re: period stretcher / expander
Post by jbdavid on Aug 3^rd, 2006, 5:01am

Now that you have your frequency, the rest can be implemented like one of the many VCO models in the examples on this site..
Phase = `m_two_pi * idtmod(Freq_out);
V(Sigout) <+ Amp*sin(Phase);// or cos(phase if you prefer..