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Design Languages >> Verilog-AMS >> If statements for compact modeling?
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Message started by skippy on Jul 29^th, 2006, 9:29pm

Title: If statements for compact modeling?
Post by skippy on Jul 29^th, 2006, 9:29pm

Are if statements a good idea for a compact model? Do model developers use if statements, smoothing functions, or something else?

Title: Re: If statements for compact modeling?
Post by Geoffrey_Coram on Jul 31^st, 2006, 6:13am

If statements aren't inherently bad, but you do have to make sure that the function -- and its derivatives! -- are continuous across the boundary.

Title: Re: If statements for compact modeling?
Post by skippy on Aug 1^st, 2006, 8:26am

Thanks for your response. It's just that I've been warned that in most circumstances that if statements typically lead to trouble. I'm writing my own modeling language, and I am just wondering if they are worth the trouble caused.

I guess I could just write a verilog parser, but I am really only interested in the analog modeling aspects. From my reading of the manual, it is hard for me to tell if you are able to access or override the symbolic derivatives which are generated. Is this possible?

Title: Re: If statements for compact modeling?
Post by Geoffrey_Coram on Aug 1^st, 2006, 10:01am

Quote:

I'm writing my own modeling language,

Why re-invent the wheel?

You almost certainly need to have if() statements; the only ones that can cause trouble are ones where the condition depends on the unknowns (voltages). Ones that depend on parameter values can't cause convergence problems, since the if() does not toggle between true and false during iterations. You'd have a very weak language if there were no if statements, and your models would run extremely slowly, because people couldn't shut off advanced model features by setting parameter switches. Eg, if you had breakdown in a diode, you calculate ISR*(exp(-(v+BV)/vt) - 1.0). Without an if() statement, you have to calculate the exponential even when ISR=0.

The symbolic derivatives can be accessed with the ddx() function. There's no way to override them; there's never a need to (except for compiler bugs).

Title: Re: If statements for compact modeling?
Post by skippy on Aug 1^st, 2006, 10:22am

Geoffrey_Coram wrote on Aug 1^st, 2006, 10:01am:

Quote:

I'm writing my own modeling language,

Why re-invent the wheel?

I started writing this thing a couple of years ago as a hobby and before I realized that the Verilog spec was available and that it had similarities to the language I created.

I am interested in source code generation and the ability to optimize derivatives in order to avoid duplicate calculations.
e.g.
ib = Is*(exp((vb-ve)/(n*VT))-1)
d_ib_d_vb = (ib+Is)/(n*VT)
d_ib_d_ve = -d_ib_d_vb

instead of the machine generated
ib = Is*(exp((vb-ve)/(n*VT))-1)
d_ib_d_vb = Is*exp((vb-ve)/(n*VT))/(n*VT)
d_ib_d_ve = -Is*exp((vb-ve)/(n*VT))/(n*VT)

and I can verify the resulting source code is correct.

Quote:

You almost certainly need to have if() statements; the only ones that can cause trouble are ones where the condition depends on the unknowns (voltages). Ones that depend on parameter values can't cause convergence problems, since the if() does not toggle between true and false during iterations. You'd have a very weak language if there were no if statements, and your models would run extremely slowly, because people couldn't shut off advanced model features by setting parameter switches. Eg, if you had breakdown in a diode, you calculate ISR*(exp(-(v+BV)/vt) - 1.0). Without an if() statement, you have to calculate the exponential even when ISR=0.

You make an interesting point about reliance on operating point, and that is something I am wrestling as to whether should be allowed. Thanks for the elaboration off of your original post.

Quote:

The symbolic derivatives can be accessed with the ddx() function. There's no way to override them; there's never a need to (except for compiler bugs).

Verilog is then insufficient for my requirements.

Title: Re: If statements for compact modeling?
Post by Geoffrey_Coram on Aug 1^st, 2006, 12:02pm

Of 3 Verilog-A compilers I know, 2 of them definitely optimize derivatives such that exp() is not repeated, and I don't actually know about the third, but I'm confident that, if it does now, it won't in the next release.

Richard Shi of U. Washington has a compiler, originally written for VHDL-AMS to Spice but I think now supporting Verilog-A also, and has shown results where his optimization techniques do *better* than the hand-generated C code from the BSIM group.

What are your requirements? You need to be able to insert incorrect derivatives? Or you think you can do a better job of optimizing the derivatives? Do you also need a compiler that allows you to change the assembly language instructions for your compact models? (Asked only somewhat jokingly.)

Title: Re: If statements for compact modeling?
Post by skippy on Aug 1^st, 2006, 1:53pm

Geoffrey_Coram wrote on Aug 1^st, 2006, 12:02pm:

Could you please send me the reference to Richard Shi's paper?

If you are fine living without the knowledge of what the model is doing with the derivatives, then I think that is just great.

Title: Re: If statements for compact modeling?
Post by Geoffrey_Coram on Aug 2^nd, 2006, 4:46am

skippy wrote on Aug 1^st, 2006, 1:53pm:

Could you please send me the reference to Richard Shi's paper?

This web site: http://www.ee.washington.edu/research/mscad/shi/mcast.html
has several references, including
L. Zhou, H. Bo, B. Wan, and C.-J. R. Shi, ``Rapid BSIM model implementation with
VHDL-AMS/Verilog-AMS and MCAST compact model compiler", pp. 285-286 in Proc. IEEE
Application Scientific Integrated Circuits/Systems-on-Chip Conf. (SOC'03), Portland, Oregon, Sept. 2003.

Quote:

If you are fine living without the knowledge of what the model is doing with the derivatives, then I think that is just great.

I've tested my compiler thoroughly. Get it right once in the compiler, and you never have to waste time checking it for every model. With some Verilog-A compilers, you can inspect the auto-generated C code (and even modify it and re-invoke the C compiler), but this isn't part of the language specification. The LRM does give you ddx() so you can get the values (not the symbolic expressions) of the derivatives, and you can $strobe or $debug the values from ddx() versus your hand calculations. Honestly, I can't see what else you really need.

Title: Re: If statements for compact modeling?
Post by rajdeep on Aug 2^nd, 2006, 5:30am

Can any of u explain to me what is this ?
if i have a verilog-A code like this..
if(V(a) > 2)
x = 1;
else
x= exp(x/$vt);

Does a successful simulation of this code require V(a) to be continuous and differentiable at V(a) = 2?
Also, what is the problem with ddx() operator in Verilog-A?? What kind of compiler problem you are talking about??
I just use verilog-A to write models..so not quite aware of this language and compiler stuff...

Title: Re: If statements for compact modeling?
Post by skippy on Aug 2^nd, 2006, 6:17am

Geoffrey_Coram wrote on Aug 2^nd, 2006, 4:46am:

skippy wrote on Aug 1^st, 2006, 1:53pm:

Could you please send me the reference to Richard Shi's paper?

If you are fine living without the knowledge of what the model is doing with the derivatives, then I think that is just great.

Thanks for the reference. My belief is that you should never have to change the compiler, only the specification of the derivatives. If the compiler creates a derivative, it is probably going to be correct, but that doesn't necessarily mean that it is the way you want it to be for that particular situation.

I've written the symbolic differentiator and the modeling language around it. I am thinking since I really want to focus on my circuit simulator, that I shouldn't spend too much time changing the modeling language I've created for it, except for adding an if statement. I'd rather focus now on implementing the harmonic balance and the noise algorithms.

I've seen these MCAST guys paper in the Circuit and Devices magazine sometime last year and I found it interesting. Are they trying to take the crown from ADMS?

Is the point that a bunch of students at Berkeley who created and prototyped a new BSIM model, wrote it inefficiently?. Now that these students have done the difficult task of inventing the model, a model compiler can now do a more optimal job at the implementation?

Title: Re: If statements for compact modeling?
Post by Geoffrey_Coram on Aug 2^nd, 2006, 8:15am

rajdeep wrote on Aug 2^nd, 2006, 5:30am:

Does a successful simulation of this code require V(a) to be continuous and differentiable at V(a) = 2?

Spice simulators generally (always?) use Newton-Raphson, and that method needs differentiability. (Of course, you could get lucky, and all the iterations could end up on one side of the discontinuity ...)

Quote:

Also, what is the problem with ddx() operator in Verilog-A?? What kind of compiler problem you are talking about??
I just use verilog-A to write models..so not quite aware of this language and compiler stuff...

No problem with the ddx() operator, it just gives you some direct access to automatically-computed derivatives. Quantities like GM and CGS are computed from derivatives, so it's helpful for design to have these values.

Title: Re: If statements for compact modeling?
Post by Geoffrey_Coram on Aug 2^nd, 2006, 8:21am

skippy wrote on Aug 2^nd, 2006, 6:17am:

I've seen these MCAST guys paper in the Circuit and Devices magazine sometime last year and I found it interesting. Are they trying to take the crown from ADMS?

Is the point that a bunch of students at Berkeley who created and prototyped a new BSIM model, wrote it inefficiently?. Now that these students have done the difficult task of inventing the model, a model compiler can now do a more optimal job at the implementation?

I'm not convinced that ADMS has the crown ... you have to use special block names for it to use in optimizing the calculations. Ie, "begin : noise" tells it that the computations in that block are used only for noise. A good compiler figures this out for itself.

Shi came to a compact model council meeting and showed these results (I haven't read the paper); he was working with BSIM3, which is fairly old and has had a fair bit of work on hand-optimizing its derivatives -- as well as a lot of work fixing errors in the derivatives. But yes, the whole idea of the Verilog-A compact modeling extensions was to remove the "grunt work" of hand-calculating and hand-optimizing derivatives, as well as writing all the other simulator interface code, so that compact modelers could focus on their work of getting the equations right.

Title: Re: If statements for compact modeling?
Post by rajdeep on Aug 2^nd, 2006, 8:49am

Quote:

This seems a bit playing with chances!!! Say, I have a sample and hold ckt, whose switch is cotrolled by a digital signal. Now this digital signal can be a sharp rise from 0 to 3V and back. Clearly if I have a statement like..
if(V(switch) > 0) V(a,b) <+ 0;
else I(a,b) <+ 0;
then it can give convergence problem because V(switch) is not differentiable at 0!!!!!
Is there a way out so that I don't need to worry about the bad chances??
Should I use filters to smoothe the transition?

Title: Re: If statements for compact modeling?
Post by jbdavid on Aug 3^rd, 2006, 4:51am

But a Sample and Hold is a Circuit, made up of "compact devices" ..
you wouldn't write a compact model of a sample and hold..
you would write a Behavioral model of a sample and hold,
OR you realize that the switch point is just GATE VOLTAGE on transistors and the GATE VOLTAGE must always be differentiable..
Compact models don't and CAN"t deal with digital signals.. they ONLY deal in voltages.
A behavioral model, if written in verilog-AMS, can.
in part because it doesn't need to be integrated into the internals of the simulator...
(once the compact model is integrated, you can use SPICE netlists to specify the design you are simulating..
nothing digital.. , you don't even need to use any verilog-A modeling in the design itself..

In mixed signal simulation, you'd use a compact model to add the EKV model to your simulator, then write a behavioral model of your sample and hold and run side by side with your transistor circuit (using your new EKV models) so that you can do characterization of the switching times, on and off resistance, and perhaps the noise..

Hope this makes it more clear..
jonathan