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Modeling >> Behavioral Models >> Behavioral Models of PLL, DAC and ADC
https://designers-guide.org/forum/YaBB.pl?num=1155608492

Message started by Jamz_will on Aug 14^th, 2006, 7:21pm

Title: Behavioral Models of PLL, DAC and ADC
Post by Jamz_will on Aug 14^th, 2006, 7:21pm

Hi,

I would like to check the behavioral models of PLL. DAC or ADC are doing the correct function.
How can i check this? Do i need also a testbench for this? What tools i need to use?

Thanks alot! ;)

Title: Re: Behavioral Models of PLL, DAC and ADC
Post by Andrew Beckett on Aug 20^th, 2006, 3:37pm

I think the responses to your post http://www.designers-guide.org/Forum/YaBB.pl?num=1154423549 will answer this.

Andrew.

Title: Re: Behavioral Models of PLL, DAC and ADC
Post by jbdavid on Aug 29^th, 2006, 10:51am

Tools: Use an AMS simulator like Cadence's AMS-Designer, Mentor's Eldo or synopsis Discovery-AMS (I use AMS-Designer, cause that what I have experience with and licenses for (needs three Spectre Tokens))

Make a schematic TB in Virtuoso..
figure out what behaviors you need to check.. (phase lock, lock time, correct output frequency for PLL?)
write Verilog-A models to check those parameters..
For the ADC you might be able to simply perform a logic (bitwise) XOR of the outputs from the circuit and behavioral model,
for the DAC you could take the difference between the two outputs.
I used an ADC as the example in my Tutorial on Verilog-AMS language given at BMAS a few years ago. so I have examples of an output comparsion block I did for the ADC there..
(Let me plug BMAS again, its coming around in just a couple of weeks Sept 14-15, REGISTER NOW!!- right after CICC (and CDNlive unfortunately the SAME time as CICC) - in Pleasant San Jose..

Jonathan