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Design >> High-Speed I/O Design >> A question on the PWD of output signal
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Message started by john_xu on Aug 17^th, 2006, 1:44am

Title: A question on the PWD of output signal
Post by john_xu on Aug 17^th, 2006, 1:44am

Hi,
I want to ask a question on the PWD. The question puzzles me for some time.

I always found the datasheet of optical receiver gives the specifications on the PWD.It is defined as the pulse width of "1"-pulse width of "0",then divided by two. The 155Mbps product I used always gives the 25ps in typ and 300ps in max, for example.

The question is I found the crossing poin of the eye-diagram for our chip is shifted up/down seriously,it sometimes even reachs to the top or bottom of the eye-diagram.But at this time, the PWD is still fall into the spec, i.e., the max PWD is still less than the 300ps in MAX as speced It is because of the rise/fall time very sharp. But the crossing point of the eye-diagram has shifted from midpoint very seriously. I want to know, is it will affect the application?Or will it affect the function of the following stage?

I am designing a optical receiver. I have completed the design. The simulation shows that the PWD in all the PVT corners is entering the spec,but some cases,the crossing points shifted seriously. So, I am not sure if my design can be freezed.May I just concern the PWD value and ignore the corossing point shiting of eye-diagram?

Thanks a lot!!!