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Design >> High-Speed I/O Design >> The peak current and vias number
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Message started by john_xu on Aug 21^st, 2006, 2:50am

Title: The peak current and vias number
Post by john_xu on Aug 21^st, 2006, 2:50am

Hi,
I have a question on the vias number and peak current.

I am designing an output inverter to drive cap load. To drive this load, the peak current is high up to ~100mA when trasistion. I found the max static current for the vias of the drain and source region is ~1mA per via. Obviously, I can not put 100 vias to tolerate this 100mA current.Then this instant current will affect the long term reliability of the device?

I know, for the VDD/GND metal width, the width is dertermined by the avarage cuurent in WCS,instead of the peak current. Is it also applicable to the VIAS?

In this case, should I put more fringers to loose the current burden?

Thanks

Title: Re: The peak current and vias number
Post by loose-electron on Aug 21^st, 2006, 1:54pm

Most foundry processes will state a min-max resistance for the vias.

Given that, you should probably determine how much additive resistance at the via point you can tolerate.

With those items in hand, you can determine the number of vias.

Also, if it is a high current design, you should probably be keeping track of the metal path resistance, it tends to add up quickly.

Jerry

Title: Re: The peak current and vias number
Post by ACWWong on Aug 21^st, 2006, 2:45pm

dandelion wrote on Aug 21^st, 2006, 2:50am:

From the aspect of lifetime/electronmigration the foundry should supply you with the max static DC current the vias can take (to guarantee x thousand hours at y degree C etc.) The figure for rms current is usually lower.
So from the aspect of peak-current, i wouldn't try to meet the rules for the peak current requirement... just meet the static reuirements.
Anyway in real layout (with resistance of tracks and vias, sub R etc.) and real PCB placement (non-ideal caps, non-zero Rs power supply etc.) the current is unlikely to peak at the same level as seen in a simulation with "ideal" sources, drives and other components. Distributed filtering effects of track parasitics are likely to limit any "spike" current as much as finite source impedance for the supply and non-ideal capacitors.
Nevertheless, you should definately consider thinking carefully about the physical no. of fingers and the best way to access the sources/drains to minimise current crowding in vias etc. and to account for the layout effects of track & via resistance. I think nice big/evenly distributed well contacts are probably in order as well if your switching large currents... see Alan Hastings' excellent book "the art of analog layout".