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Design >> High-Speed I/O Design >> duty cycle requirement for the input of CDR
https://designers-guide.org/forum/YaBB.pl?num=1156403815

Message started by john_xu on Aug 24^th, 2006, 12:16am

Title: duty cycle requirement for the input of CDR
Post by john_xu on Aug 24^th, 2006, 12:16am

Hi,
In normal conditions, what is the requirements of the duty cycles or PWD(pulse width distortion) for the input of the CDR?The input is TTL/CMOS level.

Thanks fo the help.

Title: Re: duty cycle requirement for the input of CDR
Post by loose-electron on Aug 24^th, 2006, 10:14am

John:

CDR? Could you please define?

tnx,
Jerry

Title: Re: duty cycle requirement for the input of CDR
Post by Ken Kundert on Aug 24^th, 2006, 1:17pm

CDR = Clock and Data Recovery. A key block in the receiver of a SerDes.

-Ken

Title: Re: duty cycle requirement for the input of CDR
Post by email_gz on Sep 5^th, 2006, 8:59pm

If you use only one of positive or negtive edge to Tx/RX , duty cycle ,I think , is not a big problem.
But If you use both positive and negtive edge to Tx/RX ,you should have a 50% duty cycle synchronous clock.

Title: Re: duty cycle requirement for the input of CDR
Post by ywguo on Sep 5^th, 2006, 11:38pm

John,

For a CDR, duty cycle distortion(DCD) or PWD is a part of the deterministic jitter. It reduces the sampling window, which means a smaller eye.

The total jitter, deterministic jitter + ramdom jitter should be less than the a cycle. Normally we do not have a special requirement on DCD only.

Best regards,
Yawei