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Simulators >> AMS Simulators >> sdf delays with AMS Designer
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Message started by Cri Azzolini on Aug 29^th, 2006, 2:05am

Title: sdf delays with AMS Designer
Post by Cri Azzolini on Aug 29^th, 2006, 2:05am

Hi all,
I would like to perform mixed/mode simulations (using AMS-Designer through the Hirachy-Editor->AMS-Plugin environment) including post-layout SDF delays for verilog digital modules.
From the AMS Environment User Guide, I read that it is necessary to fill the field "AMS-Plugin->AMS Options->Elaborator->SDF annotation -> Use SDF command file" but it seems to me it is not enough since the SDF delays are not considered and all the digital gates keep their original indicative delay time (e.g. 1ns as default).
I filled the field above either with the absolute path to the SDF delay file or with a file containing only the following verilog expression:

initial $sdf_annotate("sdf_delayfile.sdf", name_top_module)

I am not sure if this file can be considered a "SDF command file" but I tried anyway ;)
In both cases the sdf delays are ignored!
I also reduced the default timescale for verilog modules in order to avoid any "delay rounding" but still it does not work.

Does anybody of you experimented such behaviour? Do you have any idea?

Thanks in advance and bye!
Cri

Title: Re: sdf delays with AMS Designer
Post by ACWWong on Aug 29^th, 2006, 4:39am

in the SDF file inspect the code and make sure the forward slash is not escaped by a back slash first.

e.g.
Instance1\/Instance2\/ etc.

should be

Instance1/Instance2

doing a search and replace \/ with / worked for us... but i'm no expert on SDF files, so maybe yours is written ok....

Title: Re: sdf delays with AMS Designer
Post by Cri Azzolini on Aug 29^th, 2006, 7:17am

Hi ACWWong,
thanks for the answer but I found out that some steps are needed before to attach an SDF file to the simulation:

1) compile the SDF delay file with "ncsdfc filename.sdf" obtaining a compiled "filename.sdf.X"
2) create a SDF command file similar to the following:

// SDF command file

COMPILED_SDF_FILE = "filename.sdf.X",
SCOPE = :istance
MTM_CONTROL = "TYPICAL",

// END OF FILE

where SCOPE should be the name of the instance, to whom the SDF file is hierarchically referred to, as it appears in the top testbech file.
3) run "ncelab" with the options "-sdf_cmd_file" and "-sdf_verbose"
4) check the effectiveness of the previous step reading the logfile "sdf_annotation.log"

Unfortunately I am not able to complete this procedure beacuse I cannot find out the correct istance name for the SCOPE variable in step 2). I tried several ways but the ncelab returns to me the warning W,SDFSNF (meaning, I guess, wrong SCOPE).

Does it exist a more straightforward way to perform SDF annotation with AMS-Designer?
Did anybody make a further step?

Thanks, bye!
Cri

Title: Re: sdf delays with AMS Designer
Post by ACWWong on Aug 29^th, 2006, 8:56am

Hi Cri,

Please read my comments to your points:

1) Yes its fine to compile the SDF file yourself, but the elaborator will compile it for you automatically if can't find a compiled version.

2) Specifying the scope depends on whether you are using verilog or vhdl. If you don't specify the scope, it means you will annotate the delays on the top level... which is probably not where your digital code is....

so for verilog, assuming Instance3 is the Instance name of the digital cell:

SCOPE = Instance1.Instance2.Instance3

for vhdl

SCOPE = :Intstance1:Instance2:Instance3

You can use the hierarchy editor in "tree" view rather than "table view" to enable you to find the correct instance path for your SCOPE command.

Anyway if you
nchelp ncelab SDFSNF you will see the warning is indeed because your instance path you specified in SCOPE did not match anything in your design heirarchy. If you make them match then it should work fine.

Cheers
aw

Title: Re: sdf delays with AMS Designer
Post by Cri Azzolini on Aug 29^th, 2006, 10:05am

Hi AW,

thanks again for the reply!
It seems to work! :)

Bye,
Cri

Title: Re: sdf delays with AMS Designer
Post by qlmei on Jan 17^th, 2007, 7:05pm

Cri Azzolini wrote on Aug 29^th, 2006, 2:05am:

Hi, Cri

i tried as you said, clicking Tools/Hirachy-Editor in Virtuoso Schematic Editing, but there is no AMS-Plugin windows poping out. Could you tell me more details about that? Thanks a lot

Title: Re: sdf delays with AMS Designer
Post by Andrew Beckett on Jan 17^th, 2007, 10:55pm

Well, you need to have an installation with AMS Designer simulator in it in your UNIX path - you'll need <IUSinstDir>/tools/bin in the path, where IUSinstDir is an installation of an IUS stream (IUS583 is the current version).

Also, you'll need a license for the AMS Environment (as well as the AMS Simulator). Alternatively, you can simulate within ADE, using "ams" as the simulator choice.

It's probably worth reading the documentation and working through the tutorial (mentioned in the documentation) if you're not familiar with AMS Designer.

Regards,

Andrew.