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Design Languages >> VHDL-AMS >> simulator temperature access?
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Message started by Geoffrey_Coram on Sep 12^th, 2006, 12:31pm

Title: simulator temperature access?
Post by Geoffrey_Coram on Sep 12^th, 2006, 12:31pm

I was looking at some VHDL-AMS examples from Southampton, and the models always use a fixed temperature. Is there no way to request the simulation temperature from the simulator? Isn't this a major impediment to using VHDL-AMS models for real circuits that have to work at -40 and +125 C? Do you have to edit the model to change the temperature?

Title: Re: simulator temperature access?
Post by Andrew Beckett on Sep 20^th, 2006, 2:48am

Geoffrey,

I'm not aware of a way of doing this - there has been some discussion about this within Cadence - we have PCR 697109 asking for this. There was some talk of making it available via a package - perhaps as a package variable, but nothing definitive yet. Even then, that's not a feature of the standard, but would be implementation specific.

It does seem a bit odd that this isn't in the standard...

Regards,

Andrew.

Title: Re: simulator temperature access?
Post by Paul on Sep 22^nd, 2006, 12:53pm

Hi,

I'm not aware of anything either. Why not get in touch with someone of the standardization committee (contact information at http://www.vhdl.org/vhdl-ams)?

Paul