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Design Languages >> Verilog-AMS >> instantiating a module
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Message started by xter on Sep 22^nd, 2006, 11:39am

Title: instantiating a module
Post by xter on Sep 22^nd, 2006, 11:39am

Hello,

I am using AMS through cadence's latest ADE and am having trouble instantiating a verilogAMS module in another verilogAMS module. I know the syntax of how to do it code, but the elaborator gives me an error:

ncelab: *E,CUCFUN: instance 'f1' of the unit 'dff_va' is unresolved in '\test .stage:veriloga'.

So I'm instantiating f1 like this: dff_va f1(...). The verilogAMS modules dff_va and stage are in the same library.

Is there some seperate syntax to include a module, or does AMS have some other way of including modules?

Any help would be appreciated.

Thanks,
Xter

Title: Re: instantiating a module
Post by jbdavid on Sep 22^nd, 2006, 4:56pm

When in cadence environment, you need to have checked and saved, generated the pc.db file, master.tag,
AND have generated its Symbol..
no symbol, and the parser can't build the pc.db file of the parent cell, because its by the existance of a symbol that it knows to link this in..

OR you might have made the module name different than the cell name!!
thats a BIG no no!
jbd

Title: Re: instantiating a module
Post by Pinhead on Nov 6^th, 2006, 7:05am

I had the same error on friday, i forgot to include the library, where the module is that needs to be instantiated, in the library list in the hierarchy editor ;)