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Design Languages >> Verilog-AMS >> many modules in one cell (Virtuoso-AMS)?
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Message started by Pavel on Sep 29^th, 2006, 1:42am

Title: many modules in one cell (Virtuoso-AMS)?
Post by Pavel on Sep 29^th, 2006, 1:42am

Hello

Is it possible to create more then one module in cell.
When I do it, elaboration fails and error message appears:

*E,CUCFUN (No HDL source,0|0): instance 'I1' of the unit 'MOD2' is unresolved in 'MyLib.MOD1:verilogams'.

MOD1 consists of two MOD2.

In the cell MOD1 I created 2 modules: MOD1 and MOD2.

Thanks in advance.

Pavel.

Title: Re: many modules in one cell (Virtuoso-AMS)?
Post by bernd on Sep 29^th, 2006, 2:42am

I also saw this issue with AMS Designer when I was using
AMS Designer out of DFII with HED.
I had a Verilog file containing more than one module, specified as
'View to use from source file'.
I worked around it by importing the HDL code in a DFII library,
in my case with 'Verilog In',
then they appeared as separate modules and AMS Designer could evaluate them.

Bernd

Title: Re: many modules in one cell (Virtuoso-AMS)?
Post by jbdavid on Sep 30^th, 2006, 1:36am

Yep..
in cdba - one CELL = one Module
if you put another modele inside it needs its own module.. module name MUST match the cell name..

But this is NORMAL in verilog design.. one file per module (name.v) except gates which will all be in one library file lib.v

Of course, this is just standard practice in most places I've seen and not a requirement, and not quire often enough recommended to new users to keep it fairly universal..