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Design >> High-Speed I/O Design >> how to calculate the output impedance of an CMOS o
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Message started by phawk on Oct 1^st, 2006, 4:56pm

Title: how to calculate the output impedance of an CMOS o
Post by phawk on Oct 1^st, 2006, 4:56pm

Hi
I am new here.
Does anybody know how to calculate the output impedance of an CMOS output buffer
600/0.8(p) and 300/0.7(n)?
thanks a lot!!
phawk

Title: Re: how to calculate the output impedance of an CM
Post by SRF Tech on Oct 10^th, 2006, 7:44am

You can use basic square law equations to start. Example:
CMOS buffer, NMOS is on, PMOS is off, output is pulled to ground, ergo NMOS is in strong inversion(Vgs>Vtn)/linear region(Vds<Vdsat).
Rout = L/(W*un*Cox*(Vgs-Vtn)), likewise for a pmos.

If you interested when the gate drives of the buffer have just switched, then you would use strong inversion/active region equations.
Note that I am ignoring 1/2 half of the buffer, focusing only on either the pmos or nmos driver, assuming that both are not on simultaneously. If you have to calculate both simultaneously, then you have a more serious issue as both devices should never be on at the same time, that is how you get 'crowbar' (or 'totem pole' depending on the terminology you like) currents.

The most accurate approach is to simulate (transient) the drivers into a known load (ideal works here), probe the currents/voltages across that load and then plot your impedance over time.