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Other CAD Tools >> Physical Verification, Extraction and Analysis >> Assura LVS debugging
https://designers-guide.org/forum/YaBB.pl?num=1160022166

Message started by jak on Oct 4^th, 2006, 9:22pm

Title: Assura LVS debugging
Post by jak on Oct 4^th, 2006, 9:22pm

The LVS debugger reports that my vdd and gnd pins are "unbound" pins in my schematic. I don't know what this means. I decided to ignore this and run RCX anyway, but then vdd and gnd are not recognized as global nets and so the RCX terminates.(i have used gnd as my reference node for RC extraction mode)
Could someone please shed some light on this?

Title: Re: Assura LVS debugging
Post by bernd on Oct 5^th, 2006, 9:27am

Quote:

The LVS debugger reports that my vdd and gnd pins are "unbound" pins in
my schematic. I don't know what this means

This means that your schematic pins have no equvivalent
layout pins.
Either they are really missing, means you have not drawn them.
Or Assura does not realize them for some reasons.
but then vdd and gnd are not recognized as global nets

Quote:

Are vdd and gnd pins or globals in your schematic.

Are vdd and gnd pins or globals in your schematic.
If they are globals they should be called vdd! and gnd!
in the schematic and they also need a equvivalent in the
layout for LVS and extraction purpose.

Bernd

Title: Re: Assura LVS debugging
Post by jak on Oct 5^th, 2006, 1:57pm

Thanks for your prompt reply.
I have drawn the pins in the layout(they are metal1 pins).labelled as vdd! and gnd!

in the schematic i have used the symbols for vdd and gnd from the analog library and connected them to the transistiors.The drain (D) and source(S) nets get named as vdd! and gnd! automatically.

I even tried redrawing the schematic by removing the vdd and gnd symbols and then explicitly including vdd! and gnd! inputoutput pins.It still gave me the same error.

In the LVS debug, in the "compare" option, it does show the pins (Sch|| Lay) as 2|| 0. This makes me wonder whether the pins in the layout are actually not being detected, as you said.
But at the same time, i have 3 input and output pins each in both schematic and the layout and they don't give me errors.Actually they don't show up in the LVS debug.I assumed it was because that there was no error with it.

Thanks again for your help.

jak

Title: Re: Assura LVS debugging
Post by jak on Oct 13^th, 2006, 12:55am

hi,
i finally got it working!
apparently, i doesn't recognize pins created using "create pin instance"..when i use "create from labels" it works...that's something new i learned.thanks for replying though.

Title: Re: Assura LVS debugging
Post by aaron_do on May 10^th, 2007, 9:00pm

Hi all,

i'm getting this same error (unbounded pin). Also, creating pins from labels doesn't seem to help. Anyone know what the problem is?

thanks,
Aaron

Title: Re: Assura LVS debugging
Post by .matteo on Jun 4^th, 2007, 2:30pm

jak wrote on Oct 13^th, 2006, 12:55am:

You are right! "create pin istance" doesn't work very well... I use to create all labels and then click on "create pin from labels" and it works like a charm ;)
mat

Title: Re: Assura LVS debugging
Post by aaron_do on Jul 9^th, 2007, 11:24pm

Just thought everybody should know that for me this only seems to work when the label is on the net itself. i.e. the center of the label should overlap the net, and i think it may even have to be the same layer. Again after that you create pins from labels...

cheers,
Aaron

Title: Re: Assura LVS debugging
Post by adrianh on Oct 31^st, 2007, 1:51am

Hi, i'm also having this problem when running lvs (unbound pins). Infact, i get DRC errors too (floating gates, but goes away when i select no_erc)

i have tried the suggestions above, using create pins from layers but to no avail.

The problem however (in drc and lvs) will go away only if i use a pad for my pins :-/.

Any other advice on what i should do?

Title: Re: Assura LVS debugging
Post by MarcoC on Jan 12^th, 2011, 2:43am

Hi everybody,
I read carefully all your posts and I tried to use all the tricks you proposed but it seems they don’t work. The problem is still the same. My Assura tool doesn’t find the pins in the layout giving to me a mismatch error. Analyzing the output log it considers all the pins as unbound pins and turns out an error.
I’ve tried many tricks but nothing works.
Can you help me?

Thanks,
MarcoC

Title: Re: Assura LVS debugging
Post by gnangotzi on Oct 28^th, 2011, 1:22am

Hello everybody,
I had the same problem and eventually I've found out how to manage pins.
In virtuoso layout you should have a menu named "Hit-Kit utilities". Drop it down and select "create labels". In the "Layer" menu choose "PIN" and then the destination metal of your port . After pressing "apply" click on the pad on your layout.
That's all.
Ciao

Title: Re: Assura LVS debugging
Post by VINAY RAO on Feb 29^th, 2012, 7:33am

Hello MarcoC,
I too had the same problem. Later i realized that pin and label must be of the same metal (metal1 in my case). So first create the pin by choosing metal 1 (any of your choice ) in create->pin menu. After this you got to create label. For creating label, first select metal in LSW (as label creating menu doesn't have any option to give any metal type) and then name it. It works.

Regards,
Vinay Rao.