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Design >> High-Speed I/O Design >> latch up failure due to design ?
https://designers-guide.org/forum/YaBB.pl?num=1160065099

Message started by jason_class on Oct 5^th, 2006, 9:18am

Title: latch up failure due to design ?
Post by jason_class on Oct 5^th, 2006, 9:18am

Dear All

I need some help to understand more about latch up failure.
Usually, latch up failure happens are due to improper layout of design OR due to process issue?

I heard that often latch up failure happens in IO mos. What are they for? Why it is often the case latch up happens at IO mos? Is the W/L bigger than normal logic mos or some other reason?

If anyone has any good reference on this topic, kindly share with me.

Thank you for your help.

best rgds
Jason

Title: Re: latch up failure due to design ?
Post by loose-electron on Oct 6^th, 2006, 3:33pm

most latch problems are due to poor layoutsw without sufficient substrate contacts or well tie ups.

I/O cells are more prevalemt to the problem due to the higher currents in the circuits

http://www.fairchildsemi.com/an/AN/AN-600.pdf#search=%22%22latch%20up%22%22

See the above - it is all about keeping the IR low enough so that you do not turn on the transistors (getting Vbe over 0.6 or there abouts)

Jerry

Title: Re: latch up failure due to design ?
Post by jason_class on Oct 20^th, 2006, 11:55pm

Dear Loose e-

Good link to share. Checking it out and will be back for more...

Jason