The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> Circuit Simulators >> Negative capacitance
https://designers-guide.org/forum/YaBB.pl?num=1160834621

Message started by jefkat on Oct 14^th, 2006, 7:03am

Title: Negative capacitance
Post by jefkat on Oct 14^th, 2006, 7:03am

Hi folks,
I was simulating a transistor (65nm, with BSIM4) in cadence spectre. I did a parmteric DC run and then plotted Cgd. It was negative !
Beats me really. I guess its model thats causing prob?? Any comments?
Cheers

Title: Re: Negative capacitance
Post by achim.graupner on Oct 15^th, 2006, 10:38pm

Hi,

no worries, thats allright. Those small signal values are purely analytical and do *not* necessarily have a physical background.
They are the derivative of the charge to some terminal voltage. They describe how the charges in the variour transistor regions
are influenced by the terminal voltages.
In you case I guess it is cgd = d Q(gate) / d V(drain) . This derivative has the unit of a capacitance, hence it is named cxx.

Have a look in the manual, there should (hopefully) be a small signal equivalent circuit and the according derivation. Otherwise
have a look to the EKV model papers, there the derivations are rather easily to understand.

Good luck,
achim

Title: Re: Negative capacitance
Post by Geoffrey_Coram on Oct 16^th, 2006, 5:02am

The next-generation "PSP" model (http://pspmodel.asu.edu) addresses many of the oddities in the BSIM3/4 models such as negative capacitance.

I wouldn't say "no worries" -- there have been some convergence failures caused by negative capacitances in series with positive resistors yielding an unstable system.

Achim is right, though, that you should look in the manual, make sure that the sign conventions are what you expect. Eg, many simulators define cgd as -dQg/dVd.

Title: Re: Negative capacitance
Post by jefkat on Oct 17^th, 2006, 11:07am

Thanks much both of you. yeah in the manual the defintion is "wrong" .negative I mean
Cheers

Title: Re: Negative capacitance
Post by simon2 on Sep 20^th, 2007, 5:26pm

Hi jefkat,
dont know about 65nm, but when looking at 90nm and 180nm mos CV curves I found that spectre got it wrong, but both Hspice and WinSPICE3 got it right. At least, the results were consitent between different foundary models and matched tht measured on the bench.

For DC sims, capacitance has no practical meaning; use AC or TRAN.

Apply a voltage source to the gate using a line like:

Vg G S DC {Vgs} AC 1 PWL(0 {-dv} {dt} {dv})

For AC scale the frequency sweep for (say) 159kHz using a line like:

ac lin 2 159k 159.3k

or for TRAN scale it by choosing the parameters dv and dt, then plot the current through the capacitor for TRAN:

Cg[index] = abs(vg#branch)*{dt}/{2*dv}

or the AC output current using a line like:

Cg[index] = abs(vg#branch)/(2*PI*159.3e3)

You wont be able to do the tran version in spectre as it does not make the last simulation values available to you (at least not easily).
Hspice or WinSPICE3 do this nicely and you can be sure the results are as you would use the model in practice - there are PDKs around for well known foundries that give wildly different values for capacitance when simulated under DC, AC and Tran!

Cheers,
SimonH.

Title: Re: Negative capacitance
Post by Geoffrey_Coram on Sep 24^th, 2007, 8:59am

The transient results are probably quite hard to do, because you have to pick good values for dv and dt: small enough that you're approximating a derivative (dv -> 0) but large enough that numerical noise isn't corrupting the results.

As to your comment:

Quote:

For DC sims, capacitance has no practical meaning; use AC or TRAN.

that's not true. When computing the dc operating point (or a point along the dc sweep), the simulator can calculate the charge equations and all the derivatives; these derivatives are exactly what is used in the ac analysis. I find it quite useful when a simulator (like Spectre) provides these capacitances to be plotted for a dc sweep.

Title: Re: Negative capacitance
Post by simon2 on Oct 10^th, 2007, 6:41am

Hi Geoffrey,
I meant that at DC (0 Hz) the capacitance has no effect on current through a node. You need a change in voltage to get a response, thus only AC or Tran have any real meaning in a practical application. Agreed, you can extract all sorts of information from static models by interrogating their equations, but I am not sure to what you would apply the results. I have also found that looking at say gate capacitance under OP then sweeping bias point and taking OPs at each point generally for most simulators produces a flat line at some arbitrary capacitance value which often is grossly in error with respect to that you will get from an AC or TRAN sim at each bias point, or if you compare it to measured data for the modelled device. My guess is that the simulators are not intended to support DC or OP sims for capacitance in any serious way, as at DC (0 Hz), the result you see is possibly the product of legacy code in the underlying (SPICE) algorithm.

Cheers,
Simon2.

Title: Re: Negative capacitance
Post by Geoffrey_Coram on Oct 10^th, 2007, 11:34am

simon2 wrote on Oct 10^th, 2007, 6:41am:

I have also found that looking at say gate capacitance under OP then sweeping bias point and taking OPs at each point generally for most simulators produces a flat line at some arbitrary capacitance value which often is grossly in error with respect to that you will get from an AC or TRAN sim at each bias point, or if you compare it to measured data for the modelled device. My guess is that the simulators are not intended to support DC or OP sims for capacitance in any serious way, as at DC (0 Hz), the result you see is possibly the product of legacy code in the underlying (SPICE) algorithm.

In our internal simulator, you can run a dc sweep and plot the capacitance as a function of bias. Actually, this is the same as doing an ac analysis with a swept bias and a fixed frequency (rather than fixed bias and swept frequency, which is the usual Spice ac); the ac analysis computes the same dc operating point as the dc sweep, and then loads the capacitances (and conductances) into the complex matrix to compute ac currents. The dc sweep just omits the last step, but the operating point and capacitances are computed just as if the ac were going to be performed. I'm quite sure at least one commercial simulator does the same, and I'd be surprised if it weren't -- though some simulators make it easier to do this analysis than others.

You have to be careful about extracting the capacitance from an ac analysis, since having internal resistors (RD, RS) in the model will confuse the issue: dQg/dVd is wrt the internal drain voltage, but the voltage source is applied to the external terminal.

Designers are quite good at using small-signal quantities -- capacitances as well as conductances -- in rules of thumb for setting up their circuits.

Title: Re: Negative capacitance
Post by simon2 on Oct 11^th, 2007, 4:52am

Hi Geoffrey, re:

> You have to be careful about extracting the capacitance from an ac analysis,
> since having internal resistors (RD, RS) in the model will confuse the issue:
> dQg/dVd is wrt the internal drain voltage, but the voltage source is applied
> to the external terminal.

- are we not just interested in the imaginary part of the current?
- or did I misunderstand what you meant?

Cheers, Simon2.

Title: Re: Negative capacitance
Post by Geoffrey_Coram on Oct 11^th, 2007, 6:02am

Let me see if I can diagram this:

D -- RD -- Di -- (intrinsic device) -- Si -- RS -- S

The capacitances and conductances are computed for the intrinsic device, with respect to Di and Si. If you put a small-signal source on the drain, then the current through the device changes -- meaning that the voltage on Si changes, in addition to Di. Therefore, VGS (really, VGiSi) changes, and your ac measurement of Cgd is corrupted by some amount of Cgs (scaled by dVSi/dVD).