The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> VerilogA code for instance name and read write fil
https://designers-guide.org/forum/YaBB.pl?num=1161164544

Message started by CadenceUser888 on Oct 18^th, 2006, 2:42am

Title: VerilogA code for instance name and read write fil
Post by CadenceUser888 on Oct 18^th, 2006, 2:42am

I currently use verilogA (in cadence 2006) to simulate a component with non static internal variable that I'd like to load/store (read/write from/to a file) corresponding to its instance (number or name, like I0,I1...), since the same component is replicated many times, I don't know if it's possible to write some verilog A code and how to get the instance name from the netlist ?

Thanks

Title: Re: VerilogA code for instance name and read write
Post by Geoffrey_Coram on Oct 18^th, 2006, 6:53am

There's a percent-code, I think %m or %M, that is supposed to give you the hierarchical instance name when used in a $fprintf call.

I'm not sure if the code would also be available for $sprintf, or even if $sprintf is available to you, in order to make a filename string using the instance name.

And you might need to "fix it up" if the hierarchy specifiers are not valid as filenames.

Title: Re: VerilogA code for instance name and read write
Post by jbdavid on Oct 22^nd, 2006, 10:31am

There are also a bunch of % codes that only work when opening the file (something like %C.%r for the circuit and standard extension? %T? for the time code)
I don't know if they have been worked into the standard, but I couldn't use them on the Verilog-digital side back in 2002.

But it sounds like what you want might be better accomplished with a paramset or even a simple string parameter for the file name.
that way rather then specifiying the file per instance name, you can create all the variations of files and assign them to an instance when you put it in the schematic.
Of course in older versions of Cadence you wont be able to use string parameters
jbd

Title: Re: VerilogA code for instance name and read write
Post by CadenceUser888 on Oct 23^rd, 2006, 6:42am

yes you're right, I can do $fopen("%C") then $fdisplay, but I'm only able to write something to file, and can't read variable from it ! Because there's just no function like $fread or $fscanf in Verilog-A of Cadence (it gives syntax error). Any idea ?

Thanks

Title: Re: VerilogA code for instance name and read write
Post by Geoffrey_Coram on Oct 24^th, 2006, 4:39am

Verilog-A was based on 1364-1995 (the committee is presently updating it to 1364-2005), and that (digital) Verilog standard did not have $fread. It did have $readmemb and $readmemh, so you could try those functions...

Title: Re: VerilogA code for instance name and read write
Post by CadenceUser888 on Oct 25^th, 2006, 3:26am

Actually, I'm doing Verilog A (analog), $readmemb is only used in VerilogXL (digital)

thanks