The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Design >> High-Speed I/O Design >> Hysterisis characetristics for CMOS level output https://designers-guide.org/forum/YaBB.pl?num=1161227709 Message started by dandelion on Oct 18th, 2006, 8:15pm

Title: Hysterisis characetristics for CMOS level output Post by dandelion on Oct 18th, 2006, 8:15pm Hi, I found many product has the hysterisis characteristics with its CMOS level output(single ended). While the product with differential output has no this characteristics.I know hysterisis is important for output from chattering when the input signal is near the threshold. But I can not understand why it need not this hysterisis for differtial output? PLs. help to explain it.

Title: Re: Hysterisis characetristics for CMOS level outp Post by SRF Tech on Oct 19th, 2006, 10:53am There are many reasons for this, but we can start with a few fundamentals.  This is by no means exhaustive. Generally hysterisis is actually designed into the input/RX circuit, not the output.   Primary reason for hysterisis is to avoid erros due to issues such as signal bounce/chatter as you mentioned.  It is also used to clean up low speed or slow slewing signal curves so as to avoid nasty oscillations when the input signal is near the trigger voltage/threshold.  Another point is that with single-ended cmos, the input RX is always comparing its levels with respect to ground (wether you like it or not).  Any ground bounce or DC offsets between the grounds of the reciever and the grounds of the Transmitter, can introduce errors that are cleaned up by hysterisis.  Differential circuits, by sending complementary voltage/currents, avoid this issue and therefore have little need for hystersis in this regard. Many differential interfaces are very high speed, and slew fast enough to trigger the input reciever without worrying output oscillations/chatter.  Also most differential interfaces do not experience things such as signal bounce and so forth.  A lot of this has to do with the benefits of typical LVDS topologies that are generally clean current steering architectures into well terminated  loads.  Normal CMOS single ended IO's do not benefit form this. But what would happen if we introduced hysterisis anyway, to a differential topology.  Foremost in my mind, most high speed differential circuits use some form of clock and data recovery.  If hysterisis was built into the design, you would be introducing a tremendous amount of jitter (by design no less) that would really disturb the quality of your CDR and ruin your EYE diagrams.  Even without CDR, a differential input with hystersis would see an inordinate amount of jitter in the EYE diagram, either way, you degrad the Bit Error Rate by using hysterisis.  Short answer then is that hysterisis is actually very bad for most differential IO architectures. Other individuals may have many more insight that what I have just discussed.

Title: Re: Hysterisis characetristics for CMOS level outp Post by dandelion on Oct 23rd, 2006, 1:58am SRF Tech wrote on Oct 19th, 2006, 10:53am: There are many reasons for this, but we can start with a few fundamentals.  This is by no means exhaustive. Generally hysterisis is actually designed into the input/RX circuit, not the output.   Primary reason for hysterisis is to avoid erros due to issues such as signal bounce/chatter as you mentioned.  It is also used to clean up low speed or slow slewing signal curves so as to avoid nasty oscillations when the input signal is near the trigger voltage/threshold.  Another point is that with single-ended cmos, the input RX is always comparing its levels with respect to ground (wether you like it or not).  Any ground bounce or DC offsets between the grounds of the reciever and the grounds of the Transmitter, can introduce errors that are cleaned up by hysterisis.  Differential circuits, by sending complementary voltage/currents, avoid this issue and therefore have little need for hystersis in this regard. Many differential interfaces are very high speed, and slew fast enough to trigger the input reciever without worrying output oscillations/chatter.  Also most differential interfaces do not experience things such as signal bounce and so forth.  A lot of this has to do with the benefits of typical LVDS topologies that are generally clean current steering architectures into well terminated  loads.  Normal CMOS single ended IO's do not benefit form this. But what would happen if we introduced hysterisis anyway, to a differential topology.  Foremost in my mind, most high speed differential circuits use some form of clock and data recovery.  If hysterisis was built into the design, you would be introducing a tremendous amount of jitter (by design no less) that would really disturb the quality of your CDR and ruin your EYE diagrams.  Even without CDR, a differential input with hystersis would see an inordinate amount of jitter in the EYE diagram, either way, you degrad the Bit Error Rate by using hysterisis.  Short answer then is that hysterisis is actually very bad for most differential IO architectures. Other individuals may have many more insight that what I have just discussed. Hi SRF, Thanks for the reply. It is very helpful to me. But would you pls. further clarify a bit on more on below two items? 1."it is also used to clean up low speed or slow slewing signal curves so as to avoid nasty oscillations when the input signal is near the trigger voltage/threshold. " It is a bit difficult for me to understand it. Would you explain it a bit more detaily? 2.Here, we used "differtial circuit", "single ended circuit" to decribe our circuit. Do you mean it is for input and not output? I mean, if my citrcuit is differential input and single ended output, the circuit contains a dif-to-single converter in it. We still define it as differtial block, right? Thanks for the help.

Title: Re: Hysterisis characetristics for CMOS level outp Post by ywguo on Oct 23rd, 2006, 11:22pm Hi dandelion, First, there is noise, glitches on both edges of a signal. It makes the receiver out wrong near the input threshold. Second, we only care the input signal because it causes wrong operation of the receiver. BG Yawei

Title: Re: Hysterisis characetristics for CMOS level outp Post by SRF Tech on Oct 25th, 2006, 7:40am dandelion, I was out for a few days so I apologize for not responding sooner. Yawei comments nailed it on the head. SRF

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