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Design Languages >> Verilog-AMS >> Is this a bug of Ken's vco vams model?
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Message started by greatqs on Oct 23^rd, 2006, 7:37am

Title: Is this a bug of Ken's vco vams model?
Post by greatqs on Oct 23^rd, 2006, 7:37am

I've download the verilog-a model of vco on designers-guide.
http://www.designers-guide.org/VerilogAMS/functional-blocks/vco/vco.va
http://www.designers-guide.org/VerilogAMS/functional-blocks/vco/vco.scs

I changed some vco parameter in spectre netlist (vco.scs)
for VCO1 in vco.va file
I specify vmin=0 vmax=3.3 fmin=1 fmax=2e9
and after I run the transient simulation, I found strange result during the frequency ramping process.
as shown below
when the input voltage is large than zero, vco starts to oscillator as voltage increase as expected.
but at some time, the vco seems to stop for a while (the gap). I don't know where comes this problem, but it does bring mistakes in my pll's lockin process.

Also the verilog-a vco model intends to let real variable 'phase' (also ploted in the snapshot) integral and modulos between -pi and +pi.
But the envelop of phase's waveform said it is not.

can anyone help me out? thanks in advance!

Title: Re: Is this a bug of Ken's vco vams model?
Post by greatqs on Oct 23^rd, 2006, 7:38am

I zoom out the snapshot for detial.

Title: Re: Is this a bug of Ken's vco vams model?
Post by Ken Kundert on Oct 23^rd, 2006, 9:03am

You probably need to add a $bound_step() function to assure the simulator does not try to step over a compete cycle. I have updated the model to include it. Why don't you try downloading the latest version and trying again.

The fact that the phase does not appear to cover its full range is not a problem. It is just an artifact of the waveform being output at discrete time points.

-Ken