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Design >> High-Speed I/O Design >> the PWD vs. the TTL input level &nb
https://designers-guide.org/forum/YaBB.pl?num=1162369713

Message started by dandelion on Nov 1^st, 2006, 12:28am

Title: the PWD vs. the TTL input level &nb
Post by dandelion on Nov 1^st, 2006, 12:28am

Hi,
My circuit accepts the TTL level input, I found the PWD(pulse width distortion) degrade seriously when the input TTL level varies,because the TTL level is defined as the low is less 0.8V and the high level is larger 2V. My circuit uses 0.6um CMOS process and works in 5V supply. The PWD degradation comes from the thereshold of the input can not track the different input TTL level, it becomes worse when the edge speed of input TTL is slower.

Can anyone pls. tell me how to handle this issue?

Thanks in advance

Title: Re: the PWD vs. the TTL input level &nb
Post by loose-electron on Nov 2^nd, 2006, 8:10am

Have you considered using a comparator for your input instead of a logic gate? That way you can define the switching point thru the use of a reference voltage.

Title: Re: the PWD vs. the TTL input level &nb
Post by ywguo on Nov 8^th, 2006, 1:05am

Hi,

You have to make the edge sharp if you want to reduce the distortion or noise.

Best regards,
Yawei