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Design Languages >> Verilog-AMS >> Set Parameters with Variables ?
https://designers-guide.org/forum/YaBB.pl?num=1162824195

Message started by Pinhead on Nov 6^th, 2006, 6:43am

Title: Set Parameters with Variables ?
Post by Pinhead on Nov 6^th, 2006, 6:43am

Hi Guys,

is there any possibility to set a parameter with a variable ?

I need that for an instantiation of a verilog module in a module, i wanna overwrite the parameters of the instantiated module with a variable.

generate
genvar x
for (x=0, x< 8, x=x+1) begin: T
my_osc #(var1[x]);
end
endgenerate

Thanks!

Title: Re: Set Parameters with Variables ?
Post by Geoffrey_Coram on Nov 6^th, 2006, 12:35pm

Pinhead wrote on Nov 6^th, 2006, 6:43am:

is there any possibility to set a parameter with a variable ?

No.

Parameters must be set at elaboration time; variables aren't initialized until run time.. You have to find another way to set your parameters, not using a variable.

Title: Re: Set Parameters with Variables ?
Post by Pinhead on Nov 6^th, 2006, 11:15pm

Thank you Geoffrey!