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Design Languages >> VHDL-AMS >> VHDL and VHDL-AMS in the Cadence environment
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Message started by Eugene on Nov 11^th, 2006, 2:09pm

Title: VHDL and VHDL-AMS in the Cadence environment
Post by Eugene on Nov 11^th, 2006, 2:09pm

I am thinking about starting a major behavioral modeling project using VHDL and VHDL-AMS in the Cadence AMS environment. Does anyone have horror stories I should hear before diving in?

Also, can anyone recommend some good reference books on VHDL and VHDL-AMS. I do not care about synthesis; I need to take the language to its limits.

Title: Re: VHDL and VHDL-AMS in the Cadence environment
Post by Paul on Nov 21^st, 2006, 11:54pm

Eugene,

I haven't tried AMS Designer for simulating VHDL/VHDL-AMS models, but according to the documentation, it supports all of these.

I can strongly recommend Peter Ashenden's books on VHDL and VHDL-AMS. I tend to use them regularly when developing VHDL(-AMS) models. By coincidence (yt least AFAIK), they are entitled "The Designer's Guide to VHDL, 2nd Edition" and "The System Designer's Guide to VHDL-AMS". More information at http://www.ashenden.com.au

Good luck and please keep us updated.
Paul

Title: Re: VHDL and VHDL-AMS in the Cadence environment
Post by Eugene on Nov 22^nd, 2006, 8:32am

Paul,

Thanks for the response. I bought the VHDL book and agree that it is a very good reference. I did not know Ashenden also had a book on VHDL-AMS. I will check it outl.

I also bought Pedroni's VHDL book. I read most of Pedroni's book first. It was a good introduction for someone like me who has never used VHDL. However, Ashenden's book had a good explanation of resolved signals and resolving functions, which is one of the main reasons I'm looking into VHDL.

While shopping, I also ended up buying a book by Frevert and others entitled, "Modeling and Simulation for RF Systems Design". This book discusses applications of VHDL-AMS and VerilogA to RF systems. It also describes the elements in Cadence's rfLib, as well as the j/k bottom up models.

Anyway, thanks again for the references. I'll let you know how it goes.

-Eugene.

Title: Re: VHDL and VHDL-AMS in the Cadence environment
Post by alinalin19832007 on May 29^th, 2008, 1:25pm

My work is about developing vhdla-ms models
If you want to start developing a big project i strongly suggest you to develop the model step by step
start with a few lines , simulate it, add more lines and simulate it , if u will do it in this way u will solve from the begging the convergence problems that for sure u will met it if u will use quantities

Title: Re: VHDL and VHDL-AMS in the Cadence environment
Post by Eugene on May 30^th, 2008, 12:16am

As it turns out, I discovered that the Cadence netlister only supports those VHDL/VHDLAMS real number features common to wreals (a VerilogAMS feature). Given that Cadence's support for VerilogAMS is far deeper than its support for VHDL, I saw no point in using VHDL or VHDLAMS if I could not do anything beyond wreals.

Note: The netlister is crucial because afterall, it's the schematic we want to verify.