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Modeling >> Behavioral Models >> Simulating ESD discharge in Verilog
https://designers-guide.org/forum/YaBB.pl?num=1163503456

Message started by Dimitri on Nov 14^th, 2006, 3:24am

Title: Simulating ESD discharge in Verilog
Post by Dimitri on Nov 14^th, 2006, 3:24am

Hi,

I want to implement an ESD discharge in VerilogA
Therefor I want to have an initial condition on a capacitance ( e.g. 1 kV)

How do I state this in Verilog ? @(initial_step) ?

Regards,

Title: Re: Simulating ESD discharge in Verilog
Post by Pavel on Nov 16^th, 2006, 1:49am

There is article "Compact Modeling of On-Chip ESD Protection Devices Using Verilog-A"
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 6, JUNE 2006

that explain ESD modelling in Verilog-A. Unfortunately I can't attach it as its size is more than 500k.

Regards.

Pavel

Title: Re: Simulating ESD discharge in Verilog
Post by Geoffrey_Coram on Nov 16^th, 2006, 11:34am

Dimitri wrote on Nov 14^th, 2006, 3:24am:

How do I state this in Verilog ? @(initial_step) ?

No. Probably with analysis("ic").