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The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Simulators >> AMS Simulators >> UltraSim simulation failed https://designers-guide.org/forum/YaBB.pl?num=1163601550 Message started by Pavel on Nov 15th, 2006, 6:39am |
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Title: UltraSim simulation failed Post by Pavel on Nov 15th, 2006, 6:39am Hello Trying to run UltraSim simulation from Virtuoson Schematic Editor, I receive the following message in si.log file Running simulation in directory: "/dir1/proj/UltraSim.run1". Begin Incremental Netlisting Nov 15 15:01:22 2006 ERROR: Netlister: unable to descend into any of the views defined in the view list: "spectre cmos_sch cmos.sch schematic veriloga" for instance I1 in cell TB_0. Either add one of these views to: Library: 90131BA_DIGITAL Cell: test_case0 or modify the view list to contain an existing view. End netlisting Nov 15 15:01:22 2006 "Netlister: There were errors, no netlist was produced." Simulation did not complete. Instance I1 in TB_0 cell is verilog testbench, which I imported using icms-log/File/Import feature. Where can I find view list to add functional view? Thanks in advance Pavel |
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Title: Re: UltraSim simulation failed Post by bernd on Nov 15th, 2006, 7:25am Did you run a pure UltraSim simulation? As far as I know pure UltraSim is not able to run mix-signal simulations. What I know is that you can use a VCD file as stimulus. You should rather use the AMS designer with UltraSim as analog solver. The view list can either be changed in the Hierarchy Editor if you use a config view or in the Analog Environment "Setup -> Environmet...". But I don't think this will help you for pure UltraSim. Bernd |
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Title: Re: UltraSim simulation failed Post by Pavel on Nov 15th, 2006, 8:01am Thanks Bernd What "pure" UltraSim simulation means? Before I run UltraSim in this manner 1. Virtuoso Schematic Editor -> Tools -> Simulation -> UltraSim UltraSim menu appears 2. UltraSim -> Netlist/Simulate... Message cited in my previous message was result of these actions Now I changed approach: 1. Virtuoso Schematic Editor -> Tools -> Analog Envirnment 2. Analog Envirnment -> Setup -> Simulator/Directory/Host... - Simulator/Directory/Host... -> Simulator -> UltraSim 3. Analog Envirnment -> Setup -> Environment Switch View List: spectre cmos_sch cmos.sch schematic functional Stop View List: symbol 4. Choose Analyses -> tran, Stop Time: 10m 5. Analog Envirnment -> Netlist and Run... This provoke the following message in icms-log window: Netlist Error: The HDL cell-view "90131BA_DIGITAL" "test_case0" "functional" does not have view-specific simulation data. To create the data please open and save the view. You may also update the view by executing the following SKILL command: ahdlUpdateViewInfo("90131BA_DIGITAL" ?cell "test_case0" ?view "functional") End netlisting Nov 15 16:47:53 2006 "Netlister: There were errors, no netlist was produced." test_case0 is just verilog-coded testbench. What this error means? Regards. Pavel |
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Title: Re: UltraSim simulation failed Post by bernd on Nov 16th, 2006, 12:21am Pavel, I'm pretty certain that you can not simulate any digital HDL, Verilog or VHDL, with UltraSim and pure meant in that context ony UltraSim. For simulating Verliog with UltraSim you have to switch to AMS Desigenr and choose UltraSim as the analog sovler. (Very costly in terms of licenses) Didn't you have a transistor level representation of your Verilog block? Then you can choose a fast simulation mode in UltraSim for it, digital accurate or digital fast, this may help in term of simulation speed. Bernd |
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Title: Re: UltraSim simulation failed Post by Pavel on Nov 16th, 2006, 12:39am Thank you for answer Bernd The total design is complex. Verification with Spectre will take some days. So, I try to test it using UltraSim. It (design) consists of 2 parts - digital (schema generated from synthesis tool) and analog (made in Virtuoso Schematic Editor). Digital stimuli is coded in verilog (test_case0 module). Trying to validate UltraSim simulation (it's first time I try to use it) I didn't include analog part. So for the moment my schema consists of 2 blocks - stimuli (verilog code) and digital part (schema generated from synthesis tool). I don't have transistor level representation of verilog block as it is just stimuli. Change to AMS Designer means use AMS PlugIn in Hiearchy Editor? Regards. Pavel. |
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Title: Re: UltraSim simulation failed Post by bernd on Nov 16th, 2006, 1:56am Quote:
Yes , but depending on your your design flow is set up you might also be able to use AMS Designer out of the Analog Environment. Quote:
What does the digital part contain, if it is from the synthesis, must be a gate level netlist? What's below the gates? Should be some transistors? Bernd |
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Title: Re: UltraSim simulation failed Post by Pavel on Nov 16th, 2006, 2:51am Quote:
How? In Analog Environment window I found nothing concerning AMS. Quote:
Gates are vendor library gates. Sure, there should be gate level netlists for them. The vailable views are: symbol, msps, layout, extracted, cmos_sch, abstract. Regards. Pavel. |
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Title: Re: UltraSim simulation failed Post by bernd on Nov 16th, 2006, 3:16am Quote:
Under "Simulation -> Simulator/Directory/Host". If 'ams' is not present there it's not setup to be used inside ADE. 'cmos_sch' should be the transistor level representation of your gates. It makes me wonder why it does not work with the initial view list "spectre cmos_sch cmos.sch schematic veriloga" under UltraSim. Maybe you still have the get the Verilog stimuli into a VCD file to simulate with UltraSim alone. Bernd |
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Title: Re: UltraSim simulation failed Post by Pavel on Nov 16th, 2006, 3:44am Quote:
Yes it does present Setup -> Simulator/Directory/Host... -> Simulator -> ams. When I click on Ok, following message appears in icms-log window: *Error* You must be viewing a 'config' viewType to run Artist with ams. But I have config view for this cell..? Quote:
Yes, its true Quote:
If you mean Switch View List (Setup->Enviroment) I think it's due to the fact that my stimuli block is in verilog (functional view). Quote:
Verilog stimuli is huge, so this conversion would be combersome. Regards. Pavel. |
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Title: Re: UltraSim simulation failed Post by bernd on Nov 16th, 2006, 4:38am Quote:
You must nor only have it, you should work with it, means you should start ADE out of the schematic representation of your config view, best is have both open the HED and the schematic representation. You were prompted what to use if you try to open the config view. Verilog stimuli is huge, so this conversion would be combersome. I guess there could be a kind of automatic conversation with ncsim. To clarify things - If you want to work with UltraSim as analog solver within AMS Designer you don't have to use a VCD file for you stimulus. The the Verilog stimulus is solved by the nc part of AMS Desigenr. - If you want to use UltraSim as Fast Spice Simulator alone, it does not accept Verilog code and you have to translate your stimulus somehow. Best bet is in my opinion VCD. Bernd |
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Title: Re: UltraSim simulation failed Post by Pavel on Nov 16th, 2006, 7:02am Ok, now it's clear, thanks. I just tried this approach. 1. Run config view (Hierarchy Editor (HE) + Virtuoso Schemaic Editor (VSE)) 2. Run ADE from VSE. 3. In Setup -> Simulator/Directory/Host... -> Simulator choosed ams simulator 4. Specified simulation time. 5. Run simulation. Compilation/netlisting was OK apart from many warnings like below (is it important?). \w *WARNING* Cannot open pc.db for ("D_CELLS" "DFRS" "functional"). \w Hierarchy below (90131BA_DIGITAL.TB_0:schematic)I0.(90131BA_DIGITAL.mlx90131_topdig:schematic)u_core_u_atpg_top_u_oper_u_send_fsm_FSendS_reg_1.(D_CELLS.DFRS:functional) will not be expanded. Elaboration stopped with strage error: ncelab: *F,DLNFS: Packed library for '90131BA_simulations' was either corrupt or the file system cache consistency check failed. To correct the problem, remove the packed library, and recompile. If the problem persists, contact Cadence Design Systems. '90131BA_simulations' is library where our Spectre simulations are stocked. It isn't corrupted as we use it with Spectre. Ok, I decided to transfer cells in other project (PROJ2 for facility). In PROJ2 I did following actions: 1. Put reference to PROJ1 test_lib library in cds.lib file of PROJ2 2. Open Library Manager and copied cells from PROJ1 test_lib library into PROJ2 test_lib library 3. Removed reference to PROJ1 test_lib from PROJ2 cds.lib file. Maybe there is more smart approach to transfer cells between libraries, but I don't know it. In anyway it doesn't work. Elaborator couldn't recognize transferred cells. What I should do - recreate manually all cells in PROJ2? Regards. Pavel. |
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Title: Re: UltraSim simulation failed Post by bernd on Nov 16th, 2006, 7:40am Quote:
Can you do what the error message suggested. - cd to into the physical path of your library - remove the *.pak files - try to recompile the design Bernd |
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Title: Re: UltraSim simulation failed Post by Pavel on Nov 16th, 2006, 8:43am .pak file is removed. Now the situation is as follows: icms-log: Failed to elaborate ("90131BA_DIGITAL" "TB_0" "config"). ncelab.log: ncelab: *E,NOUNIT: Unable to find a unit named '90131BA_DIGITAL' in the libraries. ncelab: *E,NOUNIT: Unable to find a unit named '.TB_0:config' in the libraries. ncelab: *E,NOUNIT: Unable to find a unit named '90131BA_DIGITAL' in the libraries. TB_0 is the top-level testbench. It has schematic and config views. The last one I used to run simulation. '90131BA_DIGITAL' is the library where all cells are situated. What mean these elaborator errors? Regards. Pavel. |
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Title: Re: UltraSim simulation failed Post by bernd on Nov 16th, 2006, 9:10am Sorry no more glue, just can post you what nchelp returns Bernd %>nchelp ncelab NOUNIT nchelp: 05.70-s001: (c) Copyright 1995-2006 Cadence Design Systems, Inc. ncelab/NOUNIT = The specified unit does not exist in the libraries. Please check the name of the design unit and make sure that it has been compiled before rerunning ncelab. Another possibility is that the unit not found in the libraries has been compiled with a different version of the software. For example, the unit may have been compiled by the 32-bit software version but the current software version being used is the 64-bit software version. One more reason could be that the user is trying to elaborate the shell output, which is not allowed. |
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Title: Re: UltraSim simulation failed Post by Pavel on Nov 21st, 2006, 1:51am Finally the problem was resolved. It was suffucient to put cmos_sch view before functional in HE view list. So I succeded to simulate my design. But one incertitude stays. When I was controlling execution I didn't see UltraSim in the list of processes (prstat utility), but only ncsim. My actual design contains 2 parts - stimuli (coded in verilog) and digital part in the form of structural-gate transistor-level netlist from synthesis tool. I thougt that ncsim is "responsible" for stimuli and UltraSim - for digital part. Why I see only ncsim in the list of processes. Regards. Pavel. |
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Title: Re: UltraSim simulation failed Post by bernd on Nov 21st, 2006, 2:20am Because AMS Designer is a so called 'single kernel' or 'single process' mixed signal simulator. Means there is no coupled simulation and separate netlisting as used for e.g.the ' old method' Spectre-Verlog XL simulations. So ncsim is the only process but it uses the chosen analog solver method under the hood. Bernd |
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Title: Re: UltraSim simulation failed Post by Pavel on Nov 21st, 2006, 3:08am So, I have no possibility to be sure that UltraSim really run. I thought that there is some sort of high-level shell "AMS Smulator" that calls either ncsim (for verilog/VHDL) either UltraSim for transistor-level netlists. So I hoped to see ncsim and UltraSim sharing CPU, in other words I hoped to see in prstat list x1 time ncsim, then x2 time UltraSim, etc... Another question - where can I find some sort of benchmarkig of UltraSim performance I mean such shema (number of gates/transistors) + such stop time correspond to such simulation time. Why this question - I hoped that UltraSim is more rapid. Before run the simulation I set the most "rapid" settings. Regards. Pavel. |
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Title: Re: UltraSim simulation failed Post by bernd on Nov 21st, 2006, 6:05am Quote:
There is an elaborator option which indicates that the analog solver is UltraSim and which should be visible in the ncelab log file 'ncelab -amsfastspice', then trust the tool. Quote:
UltraSim Simulator User Guide, Simulation Options, located in <your_install_dir>/doc/UltraSim_User/UltraSim_User.pdf . Where <your_install_dir> is the root path to either your DFII or MMSIM installation tree. You can set the the simulation options through the Hierarchy Editor, "View -> Properties". Bernd |
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Title: Re: UltraSim simulation failed Post by Pavel on Nov 21st, 2006, 7:14am Thank you Bernd for assistance Quote:
I didn't perfectly understand what you mean. I choose UltraSim as Analog Solver in AMS Options/Simulator. What I see in ncelab.lab is: ncelab: 05.50-s008: (c) Copyright 1995-2005 Cadence Design Systems, Inc. NETZ0115 ), .RDB( _rd ), .DOUT_en( NETZ5 ), .Drive( drive ), .DIN( din ), | ncelab: *W,CSINFI (../90131BA_DIGITAL/TB_0/schematic/verilog.vams,37|39): implicit wire has no fanin (TB_0.NETZ5). ncelab: Memory Usage - 29.9M program + 47.1M data = 77.0M total ncelab: CPU Usage - 1.3s system + 2.8s user = 4.1s total (6.5s, 62.6% cpu) What means "trust the tool" As for me, benchmarking means relative estimation of performance. For my case I would like to know if simulation time is correct for my setup: My setup is as follows: 1300 gates 250 flip-flops clock1 13MHz clock2 32kHz stop time - 10ms simulation time - about 3 hours CPU - 900MHz UltraSparc UltraSim options - the most rapid What does MMSIM mean. Regards. Pavel. |
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