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Design Languages >> Verilog-AMS >> Op-amp Macro Model in ahdlLib
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Message started by hchanda on Dec 5^th, 2006, 3:42pm

Title: Op-amp Macro Model in ahdlLib
Post by hchanda on Dec 5^th, 2006, 3:42pm

Hi,

I have seen earlier postings on understanding the op-amp macro model in ahdlLib (not an ideal one).
But if I want to use it as a ideal op-amp, I defined very high gain, high input resistance, high unity gain frequency and very low output resistance .
I was using op-amp in the inverting mode , where there is a resistor between input source and in- and a feedback resistor from output to in-.
The in+ is grounded and I have also grounded the vref too.

gain=100e10
rin=100e10
rout=0
Fu=100e10

Vin=1.65V
R1=2K (between input source and in-)
Rfeedback=1K
vsupply+=1.65
vsupply-=0
Then by simulating this I would expect output to be -825mV which is not what I am getting from the model.

By looking into the verilog-A model it is not very clear to me how it is calculating the output voltage of an opamp.
Can anyone please provide the information on the calculation of opamp output voltage? (for the opamp in ahdlLib).

Thanks in advance,
hc

Title: Re: Op-amp Macro Model in ahdlLib
Post by Geoffrey_Coram on Dec 6^th, 2006, 4:18am

The opamp.va module that I see has output limiting such that the output voltage can't go (much?) below the negative supply, which in your case is 0. Hence, I would not expect an output of -825mV.

Title: Re: Op-amp Macro Model in ahdlLib
Post by hchanda on Dec 7^th, 2006, 3:10pm

Oops ! I didn't realize that I was giving 0V as negative power supply, Thank you
But still like to know how it calculates the output voltage. I appreciate your time and help
hc

Title: Re: Op-amp Macro Model in ahdlLib
Post by Geoffrey_Coram on Dec 8^th, 2006, 11:56am

I see the module contributing a current that is a gain (gm_nom) times the input voltage difference. So, I guess it's not really computing the voltage, but rather supplying a current that works with the feedback network to determine the voltage.

Title: Re: Op-amp Macro Model in ahdlLib
Post by Ken Kundert on Dec 8^th, 2006, 2:50pm

All,
Please remember that this forum is a general resource for everyone. As such, you should try to ask your questions in a way that everyone benefits from the answer. In that spirit, if you have a question or comment about a model, you should include the model here or give a pointer to where it is publicly available. If you ask about proprietary models that many visitors do not have access to, then you limit the number of people that can answer your question and the number that benefit from a response. If you really need to ask a question about a proprietary model, try to develop an abstract or alternate version that exhibits the same behavior and use that to ask your question.

Thanks,
-Ken

Title: Re: Op-amp Macro Model in ahdlLib
Post by hchanda on Dec 8^th, 2006, 5:03pm

Geoffrey thank you for the answer.

Ken, I'll take care to follow your suggestion. I completely agree with you.
The model is

// Based on the OVI Verilog-A Language Reference Manual, version 1.0 1996
//
//

`define PI 3.14159265358979323846264338327950288419716939937511

//--------------------
// opamp
//
// - operational amplifier
//
// vin_p,vin_n: differential input voltage [V,A]
// vout: output voltage [V,A]
// vref: reference voltage [V,A]
// vspply_p: positive supply voltage [V,A]
// vspply_n: negative supply voltage [V,A]
//
// INSTANCE parameters
// gain = gain []
// freq_unitygain = unity gain frequency [Hz]
// rin = input resistance [Ohms]
// vin_offset = input offset voltage referred to negative [V]
// ibias = input current [A]
// iin_max = maximum current [A]
// slew_rate = slew rate [A/F]
// rout = output resistance [Ohms]
// vsoft = soft output limiting value [V]
//
// MODEL parameters
// {none}
//

module opamp(vout, vref, vin_p, vin_n, vspply_p, vspply_n);
input vref, vspply_p, vspply_n;
inout vout, vin_p, vin_n;
electrical vout, vref, vin_p, vin_n, vspply_p, vspply_n;
parameter real gain = 835e3;
parameter real freq_unitygain = 1.0e6;
parameter real rin = 1e6;
parameter real vin_offset = 0.0;
parameter real ibias = 0.0;
parameter real iin_max = 100e-6;
parameter real slew_rate = 0.5e6;
parameter real rout = 80;
parameter real vsoft = 0.5;
real c1;
real gm_nom;
real r1;
real vmax_in;
real vin_val;

electrical cout;

analog begin

@ ( initial_step or initial_step("dc") ) begin
c1 = iin_max/(slew_rate);
gm_nom = 2 * `PI * freq_unitygain * c1;
r1 = gain/gm_nom;
vmax_in = iin_max/gm_nom;
end

vin_val = V(vin_p,vin_n) + vin_offset;

//
// Input stage.
//
I(vin_p, vin_n) <+ (V(vin_p, vin_n) + vin_offset)/ rin;
I(vref, vin_p) <+ ibias;
I(vref, vin_n) <+ ibias;

//
// GM stage with slewing
//
I(vref, cout) <+ V(vref, cout)/100e6;

if (vin_val > vmax_in)
I(vref, cout) <+ iin_max;
else if (vin_val < -vmax_in)
I(vref, cout) <+ -iin_max;
else
I(vref, cout) <+ gm_nom*vin_val ;

//
// Dominant Pole.
//
I(cout, vref) <+ ddt(c1*V(cout, vref));
I(cout, vref) <+ V(cout, vref)/r1;

//
// Output Stage.
//
I(vref, vout) <+ V(cout, vref)/rout;
I(vout, vref) <+ V(vout, vref)/rout;

//
// Soft Output Limiting.
//
if (V(vout) > (V(vspply_p) - vsoft))
I(cout, vref) <+ gm_nom*(V(vout, vspply_p)+vsoft);
else if (V(vout) < (V(vspply_n) + vsoft))
I(cout, vref) <+ gm_nom*(V(vout, vspply_n)-vsoft);
end
endmodule

Title: Re: Op-amp Macro Model in ahdlLib
Post by jbdavid on Dec 8^th, 2006, 9:31pm

The output stage is a norton equivalent circuit..
current source into a resistor.. if there is No other resistance on vout node (ie its open!)
then V(vout,ref) = V(cout,ref)
since the current source is effectively a vccs with a gain of 1/rout dependent on V(cout,ref)

Once you understand this part, you can write out a "macromodel" of the model to understand how it works
(assuming you understand macro models.. ) - but its easier to assume a bias point and do it - ignoring things (for the first cut) like the output voltage clamp..

Then you can add in the secondary effects like the voltage clamp.
Do this about 200 times, and you 'll stop writing out macromodel diagrams..
If you can't wait quite that long, you might take a look at the tool from Lynguent that will keep a schematic of the model you are writing, in parallel with the code..
Good luck

hchanda wrote on Dec 8^th, 2006, 5:03pm:

//
// Output Stage.
//
I(vref, vout) <+ V(cout, vref)/rout;
I(vout, vref) <+ V(vout, vref)/rout;

Title: Re: Op-amp Macro Model in ahdlLib
Post by smchiu on Jul 26^th, 2007, 3:46pm

Hi,

I have looked at the above code and have a question.
Under the "Dominant Pole" section, why is there two assignments to I(cout, vref)?
Sams as under the "output stage" section, two assignments to I(vref,vout) & I(vout,vref).

Thanks a lot, guys.
David.

Title: Re: Op-amp Macro Model in ahdlLib
Post by boe on Jul 27^th, 2007, 1:49am

Hi David,
Verilog-A defines that all contribution statements (assignments) to a current are added up, so under the dominant pole section, the first contribution is the Cap and the second the Res of the pole.

BOE

Title: Re: Op-amp Macro Model in ahdlLib
Post by smchiu on Jul 28^th, 2007, 7:43pm

Thanks a lot for your reply. I have also looked at this code, and came across the following line:

//
// GM stage with slewing
//
I(vref, cout) <+ V(vref, cout)/100e6;

I have been thinking for a while, but was scatching my head as to what this is actually doing. I have tried to comment this out as well, but it doesn't seem to do anything to the output.

Any one can give a hand? Thanks in advance!

Best,
David.

Title: Re: Op-amp Macro Model in ahdlLib
Post by boe on Jul 30^th, 2007, 4:10am

smchiu wrote on Jul 28^th, 2007, 7:43pm:

...
//
// GM stage with slewing
//
I(vref, cout) <+ V(vref, cout)/100e6;

I have been thinking for a while, but was scatching my head as to what this is actually doing. I have tried to comment this out as well, but it doesn't seem to do anything to the output.
...

David,
r1 is in parallel:

Code:

// Dominant Pole.
I(cout, vref) <+ V(cout, vref)/r1;

So, it doesn't do much, unless r1 is of the order of 100M...

BOE

Title: Re: Op-amp Macro Model in ahdlLib
Post by smchiu on Jul 30^th, 2007, 9:34am

HI BOE,

Thanks for your reply. I am just curious why do they put in 100e6 in the first place then? It seems it's hard-coded there. What does it represent?

Thanks.
David.

Title: Re: Op-amp Macro Model in ahdlLib
Post by boe on Aug 3^rd, 2007, 1:02am

Hi David,
smchiu wrote on Jul 30^th, 2007, 9:34am:

I am just curious why do they put in 100e6 in the first place then? It seems it's hard-coded there. What does it represent?

Good question. I suppose it's there to avoid problems if you configure the opamp such that r1 gets extremly large...
BOE

Title: Re: Op-amp Macro Model in ahdlLib
Post by X on May 19^th, 2017, 8:21am

Hi,

Did somebody who used this ahdlLib opamp had any issue to assign the slew_rate parameter in the properties?

I assigned it, but in the simulation log, it is showing always the default value of 500K. I tested higher and lower values in the slew_rate parameter field, and nothing changed.

Somebody has a clue on what is happening?

Thanks in advance for the help.

Title: Re: Op-amp Macro Model in ahdlLib
Post by Geoffrey_Coram on May 22^nd, 2017, 7:59am

Did you look at the netlist? Do you see a different value? Did you try changing the value of other parameters, and did the simulation results change?