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Design >> Mixed-Signal Design >> Digital PLL jitter performance
https://designers-guide.org/forum/YaBB.pl?num=1165599193

Message started by adesign on Dec 8^th, 2006, 9:33am

Title: Digital PLL jitter performance
Post by adesign on Dec 8^th, 2006, 9:33am

Dear all,

I'm designing a DPLL, with DCO frequency to PFD frequency ratio as 20000. With this high value of feedback divider value what would be the DPLL jitter performance and what changes should I do to improve that.

I'm planning to use 14-bit synchronous frequency divider in the feedback path.