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Simulators >> AMS Simulators >> Disable topology check in AMS Designer?
https://designers-guide.org/forum/YaBB.pl?num=1167843019

Message started by Daniel_Platte on Jan 3^rd, 2007, 8:50am

Title: Disable topology check in AMS Designer?
Post by Daniel_Platte on Jan 3^rd, 2007, 8:50am

Hi all!

This topic is related to http://www.designers-guide.org/Forum/YaBB.pl?num=1167842389/0.

When I tried to simulate the model posted within the previous topic, I achieved an error from AMS Designer's solvability check (see error message below). Nevertheless, I am pretty sure, that the DAE system is solvable. The simulator is probably confused by the "abnormal" formulation of the following equation:

(VD, ID, CJ) == proceqs(VIN, IIN, VOUT, IOUT, VD, ID, CJ, dIDdt, dVDdt) TOLERANCE "Current";

Is there a way to disable the solvability check?

Thanks for your help!
Daniel

-------------------------------------- BEGIN ERROR MESSAGE --------------------------------------------
ncvhdl diode_fulleq_seq.vhd
ncvhdl: 05.83-b001 Engineering Build Dated Fri Sep 8 18:12:42 2006 Generated on amsfarmlnx14.cadence.com: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
ARCHITECTURE dae OF mydiode IS
|
ncvhdl_p: *E,SCSUMM (diode_fulleq_seq.vhd,24|15): Solvability: Summation Check failed. 5 simultaneous statements found; 7 are required in this architecture.
-------------------------------------- END ERROR MESSAGE --------------------------------------------

Title: Re: Disable topology check in AMS Designer?
Post by Geoffrey_Coram on Jan 4^th, 2007, 5:49am

Daniel_Platte wrote on Jan 3^rd, 2007, 8:50am:

ncvhdl_p: *E,SCSUMM (diode_fulleq_seq.vhd,24|15): Solvability: Summation Check failed. 5 simultaneous statements found; 7 are required in this architecture.

This message makes it sound like there are 7 unknowns but only 5 equations, so disabling the topology check won't help you.

Perhaps your formulation is making dIDdt and dVDdt into unknowns, when they are supposed to be derivatives of other quantities?

Title: Re: Disable topology check in AMS Designer?
Post by Daniel_Platte on Jan 4^th, 2007, 6:48am

I agree on the background of the solvability check.

But the equation posted above should be accounted as three equations, as it determines three variable values (see the referenced posting in VHDL-AMS group for complete model). Also there are 7 variables and only 5 simultaneous statements, solvability should be guaranteed.

Title: Re: Disable topology check in AMS Designer?
Post by Andrew Beckett on Jan 16^th, 2007, 4:07pm

A little difficult to tell with such a small excerpt from your model - but VHDL-AMS is quite strict about needing a complete set of equations (Verilog-AMS will fill in the gaps for you in some cases). I forget the details and don't have my reference book handy - but I recall this being covered in the Ashenden et al book on VHDL-AMS http://www.amazon.com/System-Designers-VHDL-AMS-Systems-Silicon/dp/1558607498/sr=8-2/qid=1168992377/ref=sr_1_2/002-3347169-2767201?ie=UTF8&s=books

Regards,

Andrew.

Title: Re: Disable topology check in AMS Designer?
Post by Geoffrey_Coram on Jan 18^th, 2007, 4:22am

The full model is posted in this thread:
http://www.designers-guide.org/Forum/YaBB.pl?num=1167842389/0#0

I also noted there that the formulation (computing CJ instead of QJ) is not charge-conserving, though that's a separate question.